Datasheet
VDDQ
PVIN
AVIN
1
2
3
4
8
7
6
5
VSENSE
VREF
SD
GND
VTT
GND
VDDQ
PVIN
AVIN
1
2
3
4
8
7
6
5
VSENSE
VREF
SD
GND
VTT
LP2997
SNVS295F –MAY 2004–REVISED APRIL 2013
www.ti.com
Connection Diagram
Figure 2. SO PowerPAD-8 Layout Figure 3. SOIC-8 Layout
See Package Number DDA (R-PDSO-G8) See Package Number D0008A
PIN DESCRIPTIONS
SOIC-8 Pin or
Name Function
SO PowerPAD-8 Pin
1 GND Ground
2 SD Shutdown
3 VSENSE Feedback pin for regulating V
TT
.
4 VREF Buffered internal reference voltage of V
DDQ
/2
5 VDDQ Input for internal reference equal to V
DDQ
/2
6 AVIN Analog input pin
7 PVIN Power input pin
8 VTT Output voltage for connection to termination resistors
EP Exposed pad thermal connection Connect to Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)(2)
AVIN to GND −0.3V to +6V
PVIN to GND -0.3V to AVIN
VDDQ
(3)
−0.3V to +6V
Storage Temp. Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature (Soldering, 10 sec) 260°C
SOIC-8 Thermal Resistance (θ
JA
) 151°C/W
SO PowerPAD-8 Thermal Resistance (θ
JA
) 43°C/W
Minimum ESD Rating
(4)
1kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For specific specifications and test conditions
see Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.
(4) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Operating Range
Junction Temp. Range
(1)
0°C to +125°C
AVIN to GND 2.2V to 5.5V
(1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at
θ
JA
= 151.2° C/W junction to ambient with no heat sink.
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