Datasheet
V
TT
LP2996
PV
IN
V
DDQ
V
REF
AV
IN
V
REF
=
0.75V
V
SENSE
GND
+
+
+
V
DDQ
=
1.5V
V
DD
=
2.5V
V
TT
=
0.75V
SD
SD
C
IN
C
OUT
C
REF
R
1
LP2996
+
+
V
DDQ
V
DD
V
TT
V
TT
PV
IN
V
DDQ
GND
AV
IN
V
SENSE
C
OUT
C
IN
R
2
R
1
LP2996
+
+
V
DDQ
V
DD
V
TT
V
TT
PV
IN
V
DDQ
GND
AV
IN
V
SENSE
C
OUT
C
IN
R
2
LP2996-N
SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013
www.ti.com
Figure 29. Increasing VTT by Level Shifting
Conversely, the R2 resistor can be placed between V
SENSE
and V
DDQ
to shift the V
TT
output lower than the
internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below:
V
TT
= VDDQ/2 (1 - R1/R2) (12)
Figure 30. Decreasing VTT by Level Shifting
HSTL APPLICATIONS
The LP2996-N can be easily adapted for HSTL applications by connecting V
DDQ
to the 1.5V rail. This will
produce a V
TT
and V
REF
voltage of approximately 0.75V for the termination resistors. AVIN and PVIN should be
connected to a 2.5V rail for optimal performance.
Figure 31. HSTL Application
QDR APPLICATIONS
Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this
increase in bus lines has the effect of increasing the current levels required for termination. The recommended
approach in terminating multiple channels is to use a dedicated LP2996-N for each channel. This simplifies
layout and reduces the internal power dissipation for each regulator. Separate V
REF
signals can be used for each
DIMM bank from the corresponding regulator with the chipset reference provided by a local resistor divider or
one of the LP2996-N signals. Because V
REF
and V
TT
are expected to track and the part to part variations are
minor, there should be little difference between the reference signals of each LP2996-N.
14 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: LP2996-N