Datasheet

V
TT
V
REF
V
DD
R
S
R
T
CHIPSET
MEMORY
LP2995
www.ti.com SNVS190M –FEBRUARY 2002–REVISED MARCH 2013
DETAILED DESCRIPTION
The LP2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and
SSTL-3. The LP2995 is capable of sinking and sourcing current at the output V
TT
, regulating the voltage to equal
VDDQ / 2. A buffered reference voltage that also tracks VDDQ / 2 is generated on the V
REF
pin for providing a
global reference to the DDR-SDRAM and Northbridge Chipset. V
TT
is designed to track the V
REF
voltage with a
tight tolerance over the entire current range while preventing shoot through on the output stage.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting
at high frequencies encountered with DDR RAM. The most common form of termination is Class II single parallel
termination. This involves using one Rs series resistor from the chipset to the memory and one Rt termination
resistor. This implementation can be seen below in Figure 13.
Figure 13.
Typical values for R
S
and R
T
are 25 Ohms although these can be changed to scale the current requirements
from the LP2995. For determination of the current requirements of DDR-SDRAM termination please refer to the
accompanying application notes.
Pin Descriptions
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2995. AVIN is used to supply all the internal control circuitry
for the two op-amps and the output stage of V
REF
. PVIN is used exclusively to provide the rail voltage for the
output stage on the power operational amplifier used to create V
TT
. For SSTL-2 applications AVIN and PVIN pins
should be connected directly and tied to the 2.5V rail for optimal performance. This eliminates the need for
bypassing the two supply pins separately.
VDDQ
VDDQ is the input that is used to create the internal reference voltage for regulating V
TT
and V
REF
. This voltage is
generated by two internal 50kΩ resistors. This specifies that V
TT
and V
REF
will track VDDQ / 2 precisely. The
optimal implementation of VDDQ is as a remote sense for the reference input. This can be achieved by
connecting VDDQ directly to the 2.5V rail at the DIMM. This ensures that the reference voltage tracks the DDR
memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be
a 2.5V signal, which will create a 1.25V reference voltage on V
REF
and a 1.25V termination voltage at V
TT
. For
SSTL-3 applications it may be desirable to have a different scaling factor for creating the internal reference
voltage besides 0.5. For instance a typical value that is commonly used is to have the reference voltage equal
VDDQ*0.45. This can be achieved by placing a resistor in series with the VDDQ pin to effectively change the
resistor divider.
V
SENSE
The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications
the termination resistors will connect to V
TT
in a long plane. If the output voltage was regulated only at the output
of the LP2995, then the long trace will cause a significant IR drop, resulting in a termination voltage lower at one
end of the bus than the other. The V
SENSE
pin can be used to improve this performance, by connecting it to the
middle of the bus. This will provide a better distribution across the entire termination bus.
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