Datasheet

LMZ35003
www.ti.com SNVS988 –JULY 2013
PIN DESCRIPTIONS
TERMINAL
DESCRIPTION
NAME NO.
1
4
5
These pins are connected to the internal analog ground (AGND) of the device. This node should be treated
as the zero volt ground reference for the analog control circuitry. Pad 37 should be connected to PCB
30
AGND ground planes using multiple vias for good thermal performance. Not all pins are connected together
32
internally. All pins must be connected together externally with a copper plane or pour directly under the
module. Connect AGND to PGND at a single point (GND_PT; pins 8 & 9). See Layout Recommendations.
33
34
37
2
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These
DNC 3
pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
25
6
7
21
22
Phase switch node. Do not place any external component on these pins or tie them to a pin of another
PH
function.
23
24
38
41
8
Ground Point. Connect AGND to PGND at these pins as shown in the Layout Considerations. These pins
GND_PT
are not connected to internal circuitry, and are not connected to one other.
9
10
11
12
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output
VOUT 13 load and connect external bypass capacitors between these pins and PGND. Connect a resistor from these
pins to VADJ to set the output voltage.
14
15
39
16
17
This is the return current path for the power stage of the device. Connect these pins to the load and to the
18
PGND bypass capacitors associated with VIN and VOUT. Pad 40 should be connected to PCB ground planes using
19
multiple vias for good thermal performance.
20
40
Input voltage. This pin supplies all power to the converter. Connect this pin to the input supply and connect
VIN 26
bypass capacitors between this pin and PGND.
Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to control
INH/UVLO 27
the INH function. A resistor divider between this pin, AGND, and VIN sets the UVLO voltage.
Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.
SS/TR 28
A voltage applied to this pin allows for tracking and sequencing control.
Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this
STSEL 29
pin open to enable the TR feature.
This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An
RT/CLK 31 external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be
used to synchronize to an external clock.
Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately
PWRGD 35
±6% out of regulation. A pull-up resistor is required.
VADJ 36 Connecting a resistor between this pin and VOUT sets the output voltage.
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