Datasheet

PWRGD
VIN
PGND
PH
VOUT
RT/CLK
VADJ
STSEL
SS/TR
LMZ35003
PWRGD
Logic
+
+
VREF Comp
Power
Stage
and
Control
Logic
Thermal Shutdown
Shutdown
Logic
OCP
VIN
UVLO
OSC w/PLL
AGND
INH/UVLO
LMZ35003
SNVS988 –JULY 2013 www.ti.com
THERMAL INFORMATION
LMZ35003
THERMAL METRIC
(1)
RKG UNIT
41 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
14
ψ
JT
Junction-to-top characterization parameter
(3)
3.3 °C/W
ψ
JB
Junction-to-board characterization parameter
(4)
6.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance, θ
JA
, applies to devices soldered directly to a 100 mm x 100 mm double-sided, 4-layer PCB
with 1 oz. copper and natural convection cooling. Additional airflow reduces θ
JA
.
(3) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature, T
J
, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). T
J
= ψ
JT
* Pdis + T
T
; where Pdis is the power dissipated in the device and T
T
is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature, T
J
, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). T
J
= ψ
JB
* Pdis + T
B
; where Pdis is the power dissipated in the device and T
B
is
the temperature of the board 1mm from the device.
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
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