Datasheet

AGND
RT/CLK
R
RT
External Clock
300 kHz to 1 MHz
1 kΩ
470 pF
0
100
200
300
400
500
600
700
800
900
10 15 20 25 30 35 40 45 50
Input Voltage (V)
Output Current (mA)
2.5 V, 400 kHz
3.3 V, 400 kHz
5.0 V, 400 kHz
9 V, 600 kHz
12 V, 800 kHz
15 V, 1 MHz
G000
LMZ35003
www.ti.com SNVS988 –JULY 2013
Light-Load Behavior
The LMZ35003 is a non-synchronous converter. One of the characteristics of a non-synchronous converter is
that as the load current on the output is decreased, a point is reached where the energy delivered by a single
switching pulse is more than the load can absorb. This causes the output voltage to rise slightly. This rise in
output voltage is sensed by the feedback loop and the device responds by skipping one or more switching cycles
until the output voltages falls back to the set point. At very light loads or no load, many switching cycles are
skipped. The observed effect during this pulse skipping mode of operation is an increase in the peak to peak
ripple voltage, and a decrease in the ripple frequency. The load current where pulse skipping begins is a function
of the input voltage, the output voltage, and the switching frequency. A plot of the pulse skipping threshold
current as a function of input voltage is given in Figure 38 for a number of popular output voltage and switching
frequency combinations.
Figure 38. Pulse Skipping Threshold
Synchronization (CLK)
An internal phase locked loop (PLL) allows synchronization between 400 kHz and 1 MHz, and to easily switch
from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to
the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8
V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In
applications where both RT mode and CLK mode are needed, the device can be configured as shown in
Figure 39.
Before the external clock is present, the device works in RT mode where the switching frequency is set by the
R
RT
resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK
pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not
recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100
kHz first before returning to the switching frequency set by the R
RT
resistor .
Figure 39. CLK/RT Configuration
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