Datasheet

LMZ34002
www.ti.com SNVS989A –JULY 2013–REVISED SEPT 2013
ELECTRICAL CHARACTERISTICS
-40°C ≤ T
A
≤ +85°C, V
IN
= 12 V, V
OUT
= –5.0 V, I
OUT
= 2.0A
C
IN
= 2 x 2.2 µF ceramic, C
OUT
= 2 x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OUT
Output current Over input voltage and output voltage range 0
(1)
2.0
(2)
A
V
IN
Input voltage range Over output current range 4.5 40
(3)
V
UVLO V
IN
Undervoltage lockout Rising only, R
UVLO1
= 174 kΩ, R
UVLO2
= 63.4 kΩ 4.5 V
V
OUT(adj)
Output voltage adjust range Over output current range –3.0 –17
(3)
V
Set-point voltage tolerance T
A
= 25°C, I
OUT
= 100 mA 2.0%
(4)
Temperature variation –40°C ≤ T
A
≤ +85°C ±0.5% ±1.0%
V
OUT
Line regulation Over input voltage range ±0.1%
Load regulation From 100 mA to I
OUT(max)
±0.4%
Total output voltage variation Includes set-point, line, load, and temperature variation 3.0%
(4)
V
OUT
= –12 V, I
OUT
= 1.0 A 85 %
V
IN
= 24 V V
OUT
= –5.0 V, I
OUT
= 1.0 A 81 %
V
OUT
= –3.3 V, I
OUT
= 1.0 A 77 %
η Efficiency
V
IN
= 12 V V
OUT
= –12 V, I
OUT
= 0.6 A 86 %
V
OUT
= –5.0 V, I
OUT
= 1.0 A 81 %
V
OUT
= –3.3 V, I
OUT
= 1.0 A 78 %
Output voltage ripple 20 MHz bandwith, 100 mA ≤ I
OUT
≤ I
OUT(max)
1% V
OUT
I
LIM
Current limit threshold 3.0
(5)
A
Recovery time 500 µs
1.0 A/µs load step from 25 to 75%
Transient response
I
OUT(max)
V
OUT
over/undershoot 80 mV
V
INH
Inhibit threshold voltage INH with respect to A_VOUT 1.15 1.25 1.36
(6)
V
V
INH
< 1.15 V –0.9 μA
I
INH
INH Input current
V
INH
> 1.36 V –3.8 μA
I
I(stby)
Input standby current INH pin to A_VOUT 1.3 4 µA
f
SW
Switching frequency RT pin to A_VOUT 700 800 900 kHz
R
RT
= 0 Ω 700
(7)
900
(7)
kHz
f
CLK
Synchronization frequency
R
RT
= 93.1 kΩ 400
(7)
600
(7)
kHz
V
CLK-H
CLK High-Level Threshold With respect to A_VOUT 1.9 2.2 V
V
CLK-L
CLK Low-Level Threshold With respect to A_VOUT 0.5 0.7 V
D
CLK
CLK Duty cycle 25% 50% 75%
Thermal shutdown 180 °C
Thermal Shutdown
Thermal shutdown hysteresis 15 °C
Ceramic 4.7
(8)
10
C
IN
External input capacitance µF
Non-ceramic 22
C
OUT
External output capacitance 100
(9)
430
(9)
µF
(1) This device can regulate V
OUT
down to 0 A, however the ripple may increase due to pulse-skipping at light loads. See Light-Load
Behavior for more information. See No-Load Operation when operating at 0 A.
(2) The maximum current is dependant on V
IN
and V
OUT
, see Figure 33.
(3) The sum of V
IN
+ |V
OUT
| must not exceed 50 V.
(4) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external R
SET
resistor.
(5) This product is not designed to endure a sustained (> 5 sec) over-current condition.
(6) If this pin is left open circuit, the device operates when input power is applied. An external level-shifter is required to interface with this
pin. See Output On/Off Inhibit (INH) for further guidance.
(7) The synchronization frequency is dependant on V
IN
and V
OUT
as shown in Switching Frequency. R
RT
must be either 0 Ω or 93.1kΩ.
(8) A minimum of 4.7 µF of ceramic external capacitance is required across the input (VIN and PGND connected) for proper operation.
Locate the capacitor close to the device. See Table 1 for more details.
(9) The amount of required capacitance must include at least 2 x 47 µF ceramic capacitor (or 4 x 22 µF). Locate the capacitance close to
the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 1 for
more details. See Inrush Current section when adding additional output capacitance.
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