Datasheet
A_VOUTRT
93.1k
CLK
External Clock
400 kHz to 600 kHz
1 kΩ
470 pF
GND
3.3 V
BAV99
BAV99
A_VOUT
CLK
External Clock
700 kHz to 900 kHz
1 kΩ
470 pF
GND
3.3 V
RT
BAV99
BAV99
RT
R
RT
A_VOUT
LMZ34002
SNVS989A –JULY 2013–REVISED SEPT 2013
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Switching Frequency
The recommended switching frequency of the LMZ34002 is 800 kHz. To operate at the recommended switching
frequency, connect the RT pin (Pin 30) to A_VOUT (at pin 32).
It is recommended to adjust the switching frequency in applications with both, higher input voltage (> 18V) and
lower output voltage (< –8V). For these applications, improved operating performance can be obtained by
decreasing the operating frequency to 500 kHz by adding a resistor, R
RT
of 93.1 kΩ between the RT pin and
A_VOUT as shown in Figure 38. Figure 39 shows the recommended switching frequency over input voltage and
output voltage.
Figure 38. R
RT
Resistor Placement Figure 39. Recommended Switching Frequency
Table 5. Standard Resistor Values For Setting Switching Frequency
f
SW
(kHz) 500 800
R
RT
(kΩ) 93.1 0 (short)
Synchronization (CLK)
An internal phase locked loop (PLL) allows synchronization from 700 kHz to 900 kHz for 800 kHz applications, or
400 kHz to 600 kHz for 500 kHz applications. See Figure 39 to determine switching frequency based on input
voltage and output voltage. To implement the synchronization feature, connect a square wave clock signal to the
RT/CLK pin with a duty cycle between 25% to 75%. The clock signal amplitude must transition lower than 0.5 V
and higher than 2.2 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In
applications requiring CLK mode, configure the device as shown in Figure 40 (800 kHz) and Figure 41 (500kHz).
Before the external clock is present, the device works in RT mode where the switching frequency is set by the
R
RT
resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK
pin is pulled above the RT/CLK high threshold (2.2 V), the device switches from RT mode to CLK mode and the
CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not
recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100
kHz first before returning to the switching frequency set by the RT resistor.
Figure 40. CLK Configuration (800 kHz Typ) Figure 41. CLK Configuration (500 kHz Typ)
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