Datasheet

LMZ31710
www.ti.com SNVS987A –JULY 2013–REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
Over –40°C to 85°C free-air temperature, PV
IN
= V
IN
= 12 V, V
OUT
= 1.8 V, I
OUT
= 10 A,
C
IN
= 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, C
OUT
= 4 x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OUT
Output current T
A
= 85°C, natural convection 0
(1)
10 A
V
IN
Input bias voltage range Over output current range 4.5 17 V
PV
IN
Input switching voltage range Over output current range 2.95
(2)
17
(3)
V
V
IN
Increasing 4.0 4.5
UVLO V
IN
Undervoltage lockout V
V
IN
Decreasing 3.5 3.85
V
OUT(adj)
Output voltage adjust range Over output current range 0.6 5.5 V
Set-point voltage tolerance T
A
= 25°C, I
OUT
= 0 A ±1%
(4)
Temperature variation –40°C ≤ T
A
≤ +85°C, I
OUT
= 0 A ±0.2%
V
OUT
Line regulation Over input voltage range ±0.1%
Load regulation Over output current range ±0.2%
Total output voltage variation Includes set-point, line, load, and temperature variation ±1.5%
(4)
V
OUT
= 5.0 V, f
SW
= 1 MHz 93 %
V
OUT
= 3.3 V, f
SW
= 750 kHz 92 %
V
OUT
= 2.5 V, f
SW
= 750 kHz 90 %
P
VIN
= V
IN
= 12 V
V
OUT
= 1.8 V, f
SW
= 500 kHz 89 %
I
O
= 5 A
V
OUT
= 1.2 V, f
SW
= 300 kHz 86 %
V
OUT
= 0.9 V, f
SW
= 250 kHz 84 %
η Efficiency V
OUT
= 0.6 V, f
SW
= 200 kHz 81 %
P
VIN
= V
IN
= 5 V V
OUT
= 3.3 V, f
SW
= 750 kHz 94 %
I
O
= 5 A
V
OUT
= 2.5 V, f
SW
= 750 kHz 93 %
V
OUT
= 1.8 V, f
SW
= 500 kHz 92 %
V
OUT
= 1.2 V, f
SW
= 300 kHz 89 %
V
OUT
= 0.9 V, f
SW
= 250 kHz 87 %
V
OUT
= 0.6 V, f
SW
= 200 kHz 83 %
Output voltage ripple 20 MHz bandwith 14 mV
P-P
ILIM pin open 15 A
I
LIM
Current limit threshold
ILIM pin to AGND 12 A
Recovery time 100 µs
1.0 A/µs load step from
Transient response
25 to 75% I
OUT(max)
VOUT over/undershoot 80 mV
Inhibit High Voltage 1.3 open
(5)
V
INH
Inhibit threshold voltage V
Inhibit Low Voltage -0.3 1.1
INH Input current V
INH
< 1.1 V -1.15 μA
I
INH
INH Hysteresis current V
INH
> 1.3 V -3.3 μA
I
I(stby)
Input standby current INH pin to AGND 2 10 µA
Good 95%
V
OUT
rising
Fault 108%
PWRGD Thresholds
Power Good Fault 91%
V
OUT
falling
Good 104%
PWRGD Low Voltage I(PWRGD) = 0.5 mA 0.3 V
f
SW
Switching frequency R
RT
= 169 kΩ 400 500 600 kHz
f
CLK
Synchronization frequency 200 1200 kHz
V
CLK-H
CLK High-Level 2.0 5.5 V
CLK Control
V
CLK-L
CLK Low-Level 0.5 V
D
CLK
CLK Duty Cycle 20 50 80 %
(1) See Light Load Efficiency (LLE) section for more information for output voltages < 1.5 V.
(2) The minimum P
VIN
is 2.95 V or (V
OUT
+ 0.7 V), whichever is greater. See Table 9 for more details.
(3) The maximum PV
IN
voltage is 17 V or (22 x V
OUT
), whichever is less. See Table 9 for more details.
(4) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external R
SET
resistor.
(5) Value when no voltage divider is present at the INH/UVLO pin. This pin has an internal pull-up. If it is left open, the device operates
when input power is applied. A small, low-leakage MOSFET is recommended for control. Do not tie this pin to VIN.
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