Datasheet

LMZ31710
SNVS987A –JULY 2013–REVISED JULY 2013 www.ti.com
Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 46 thru
Figure 49, shows a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another.
• Place R
SET
, R
RT
, and C
SS
as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
Figure 46. Typical Top-Layer Layout Figure 47. Typical Layer-2 Layout
Figure 48. Typical Layer 3 Layout Figure 49. Typical Bottom-Layer Layout
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