Datasheet

LMZ31710

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SNVS987A –JULY 2013–REVISED JULY 2013

VIN and PVIN Input Voltage

The LMZ31710 allows for a variety of applications by using the VIN and PVIN pins together or separately. The

VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the

power converter system.

If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 17 V. If using the VIN

pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range from as

low as 2.95 V to 17 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12 V, for

best performance. A voltage divider connected to the INH/UVLO pin can adjust either input voltage UVLO

appropriately. See the Programmable Undervoltage Lockout (UVLO) section of this datasheet for more

information.

3.3 V PVIN Operation

Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN

from 5 V to 12 V, for best performance. See application note, SNVA692 for help creating 5 V from 3.3 V using a

small, simple charge pump device.

Power Good (PWRGD)

The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 95% and 104% of the

set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is

between 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once

VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current

sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is

lower than 91% or greater than 108% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input

UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.

Light Load Efficiency (LLE)

The LMZ31710 operates in pulse skip mode at light load currents to improve efficiency and decrease power

dissipation by reducing switching and gate drive losses.

These pulses may cause the output voltage to rise when there is no load to discharge the energy. For output

voltages < 1.5 V, a minimum load is required. The amount of required load can be determined by Equation 2. In

most cases the minimum current drawn by the load circuit will be enough to satisfy this load. Applications

requiring a load resistor to meet the minimum load, the added power dissipation will be ≤ 3.6 mW. A single 0402

size resistor across VOUT and PGND can be used.

(2)

When V

OUT

= 0.6 V and R

SET

= OPEN, the minimum load current is 600 µA.

SYNC_OUT

The LMZ31710 provides a 180° out-of-phase clock signal for applications requiring synchronization. The

SYNC_OUT pin produces a 50% duty cycle clock signal that is the same frequency as the device's switching

frequency, but is 180° out of phase. Operating two devices 180° out of phase reduces input and output voltage

ripple. The SYNC_OUT clock signal is compatible with other LMZ3 devices that have a CLK input.

Product Folder Links: LMZ31710