Datasheet

LMZ31704
SLVSBV8A –JUNE 2013–REVISED AUGUST 2013 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over –40°C to 85°C free-air temperature, PV
IN
= V
IN
= 12 V, V
OUT
= 1.8 V, I
OUT
= 4 A,
C
IN
= 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, C
OUT
= 4 x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
CLK
Synchronization frequency 200 1200 kHz
V
CLK-H
CLK High-Level 2.0 5.5 V
CLK Control
V
CLK-L
CLK Low-Level 0.5 V
D
CLK
CLK Duty Cycle 20 50 80 %
Thermal shutdown 175 °C
Thermal Shutdown
Thermal shutdown hysteresis 10 °C
Ceramic 44
(6)
C
IN
External input capacitance µF
Non-ceramic 100
(6)
Ceramic 47
(7)
200 1500
µF
C
OUT
External output capacitance Non-ceramic 220
(7)
5000
(8)
Equivalent series resistance (ESR) 35 mΩ
(6) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An
additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the
PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails,
place 4.7µF of ceramic capacitance directly at the VIN pin. See Table 6 for more details.
(7) The amount of required output capacitance varies depending on the output voltage (see Table 5 ). The amount of required capacitance
must include at least 1x 47µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the
load improves the response of the regulator to load transients. See Table 5 and Table 6 more details.
(8) When using both ceramic and non-ceramic output capacitors, the combined maximum must not exceed 5000 µF. It may be necessary to
increase the slow start time when turning on into the maximum capacitance. See the Slow Start (SS/TR) section for information on
adjusting the slow start time.
THERMAL INFORMATION
LMZ31704
THERMAL METRIC
(1)
RVQ42 UNIT
42 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
13.3
ψ
JT
Junction-to-top characterization parameter
(3)
1.6 °C/W
ψ
JB
Junction-to-board characterization parameter
(4)
5.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, literature
number SPRA953.
(2) The junction-to-ambient thermal resistance, θ
JA
, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with
2 oz. copper and natural convection cooling. Additional airflow reduces θ
JA
.
(3) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature, T
J
, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). T
J
= ψ
JT
* Pdis + T
T
; where Pdis is the power dissipated in the device and T
T
is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature, T
J
, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). T
J
= ψ
JB
* Pdis + T
B
; where Pdis is the power dissipated in the device and T
B
is
the temperature of the board 1mm from the device.
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