Datasheet

V
IN
4.5 V to 17 V
C
IN3
4.7 µF
LMZ31704
PWRGD
SENSE+
VOUT
VIN
PVIN
INH/UVLO
RT/CLK
C
IN2
47 µF
VADJ
SS/TR
STSEL AGND PGND
C
IN1
100 µF
R
SET
2.15 k
+
C
OUT1
3x 100 µF
C
OUT2
220 µF
V
OUT
1.0 V
+
P
VIN
3.3 V
R
RT
1 M
ISHARE
SYNC_OUT
C
IN3
0.1 µF
LMZ31704
SLVSBV8A –JUNE 2013–REVISED AUGUST 2013 www.ti.com
Figure 23. Typical Schematic
PVIN = 3.3 V, VIN = 4.5 V to 17 V, VOUT = 1.0 V
VIN and PVIN Input Voltage
The LMZ31704 allows for a variety of applications by using the VIN and PVIN pins together or separately. The
VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the
power converter system.
If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 17 V. If using the VIN
pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range from as
low as 2.95 V to 17 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12 V, for
best performance. A voltage divider connected to the INH/UVLO pin can adjust either input voltage UVLO
appropriately. See the Programmable Undervoltage Lockout (UVLO) section of this datasheet for more
information.
3.3 V PVIN Operation
Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN
from 5 V to 12 V, for best performance. See application note,SNVA692 for help creating 5 V from 3.3 V using a
small, simple charge pump device.
Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 95% and 104% of the
set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is
between 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once
VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current
sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is
lower than 91% or greater than 108% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input
UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.
SYNC_OUT
The LMZ31704 provides a 180° out-of-phase clock signal for applications requiring synchronization. The
SYNC_OUT pin produces a 50% duty cycle clock signal that is the same frequency as the device's switching
frequency, but is 180° out of phase. Operating two devices 180° out of phase reduces input and output voltage
ripple. The SYNC_OUT clock signal is compatible with other LMZ3 devices that have a CLK input.
16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMZ31704