Datasheet

LMZ31530
SLVSBC7B –OCTOBER 2013–REVISED DECEMBER 2013 www.ti.com
ELECTRICAL CHARACTERISTICS
T
A
= -40°C to 85°C, PVIN = VIN = 12 V, VOUT = 1.8 V, I
OUT
= 30A
C
IN
= 2x 22 µF ceramic & 330 µF bulk, C
OUT
= 4x 100 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OUT
Output current 0 30 A
V
IN
Input bias voltage range Over I
OUT
range 4.5 14.5 V
P
VIN
Input switching voltage range Over I
OUT
range 3.0
(1)
14.5 V
V
IN
Increasing 4.0 4.2 4.33 V
UVLO VIN Undervoltage lockout
Hysteresis 0.25
V
OUT(adj)
Output voltage adjust range Over I
OUT
range 0.6 3.6 V
Set-point voltage tolerance ±1.0%
(2)
Temperature variation -40°C ≤ T
A
≤ +85°C ±0.25%
V
OUT
Load regulation Over I
OUT
range +0.4%
Total output voltage variation Includes set-point, load, and temperature variation ±2.0%
(2)
P
VIN
±10% ±0.1%
Line regulation
Over P
VIN
range ±0.7%
V
OUT
= 3.3 V, f
SW
= 500kHz 94
V
OUT
= 1.8 V, f
SW
= 500kHz 92
P
VIN
= V
IN
= 12 V
V
OUT
= 1.2 V, f
SW
= 500kHz 88 %
I
O
= 15 A
V
OUT
= 0.9 V, f
SW
= 500kHz 86
V
OUT
= 0.6 V, f
SW
= 500kHz 82
η Efficiency
P
VIN
= V
IN
= 5 V V
OUT
= 3.3 V, f
SW
= 500kHz 96
I
O
= 15 A
V
OUT
= 1.8 V, f
SW
= 500kHz 94
V
OUT
= 1.2 V, f
SW
= 500kHz 91 %
V
OUT
= 0.9 V, f
SW
= 500kHz 88
V
OUT
= 0.6 V, f
SW
= 500kHz 85
Output voltage ripple 20 MHz bandwith 1% VOUT
I
LIM
Current limit threshold 40 A
Recovery time 30 µs
2.5 A/µs load step from 25 to 75%
Transient response
IOUT
(max)
VOUT over/undershoot 30 mV
Inhibit High Voltage 1.8 Open
(3)
V
V
INH
Inhibit Control
Inhibit Low Voltage -0.3 0.6 V
V
IN
= 5 V 0.5 0.7 mA
I
IN(stby)
VIN standby current INH pin to AGND
V
IN
= 12 V 1.2 1.5 mA
Good 95
V
OUT
rising
Fault 115
PWRGD Thresholds %
Power Good Fault 90
V
OUT
falling
Good 110
PWRGD Low Voltage I(PWRGD) = 2 mA 0.2 0.3 V
f
SW
Switching frequency FREQ_SEL pin OPEN, I
OUT
= 10 A 470 520 570 kHz
66 kΩ resistor between FREQ_SEL pin and PGND 300 kHz
f
SEL
Frequency Select
(4)
FREQ_SEL pin connected to V5V (pin 61) 850 kHz
Thermal shutdown 145 °C
Thermal Shutdown
Thermal shutdown hysteresis 10 °C
Ceramic 44
(5)
94
C
IN
External input capacitance µF
Non-ceramic 330
(1) The minimum PVIN voltage is 3.0V or (V
OUT
+ 1.1V), whichever is greater. See VIN and PVIN Input Voltage for more details.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external R
SET
resistor.
(3) This pin has an internal pull-up. If this pin is left open circuit, the device operates when a valid input voltage is applied. A small, low-
leakage (<300nA) MOSFET is recommended for control.
(4) See the Frequency Select section for more information on selecting the frequency.
(5) A minimum of 44 µF (2x 22 µF) of external ceramic capacitance is required across the input (PVIN/VIN and PGND connected) for
proper operation. Locate the capacitor close to the device. See Table 3 for more details. When operating with split VIN and PVIN rails,
place 4.7 µF of ceramic capacitance directly at the VIN pin to PGND.
4 Copyright © 2013, Texas Instruments Incorporated
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