Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- THERMAL INFORMATION
- PACKAGE SPECIFICATIONS
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS (PVIN = VIN = 12 V) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to , , and . The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm six-layer PCB with 1 oz. copper. Applies to , , and .
- TYPICAL CHARACTERISTICS (PVIN = VIN = 5 V) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to , , and . The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm six-layer PCB with 1 oz. copper. Applies to , , and .
- APPLICATION INFORMATION
- ADJUSTING THE OUTPUT VOLTAGE
- Frequency Select
- CAPACITOR RECOMMENDATIONS FOR THE LMZ31530 POWER SUPPLY
- Transient Response
- Transient Waveforms Device configured for FCCM mode of operation, (pin 3 connected to pin 19).
- Application Schematics
- VIN and PVIN Input Voltage
- 3.3 V PVIN Operation
- Power Good (PWRGD)
- Slow Start (SS_SEL)
- Auto-Skip Eco-Mode / Forced Continuous Conduction Mode
- Power-Up Characteristics
- Pre-Biased Start-Up
- Remote Sense
- Output On/Off Inhibit (INH)
- Overcurrent Protection
- Current Limit (ILIM) Adjust
- Thermal Shutdown
- Layout Considerations
- EMI
- Revision History
LMZ31530
SLVSBC7B –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com
Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 28 thru
Figure 33, shows a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another. AGND should only be used as the return for R
SET
.
• Place R
SET
, R
FREQ
, and R
SS
as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
Figure 28. Typical Top Layer Layout Figure 29. Typical Layer 2 Layout
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Product Folder Links: LMZ31530