Datasheet

AGND
PH
VOUT
PGND
VIN/PVIN
C
IN2
R
SET
R
RT
C
OUT1
SENSE+
Via
SENSE+
Via
C
OUT3
C
IN1
C
SS
C
OUT2
AGND to PGND
connection
SENSE+
Via
SENSE+
Via
AGND
Plane
PGND
Plane
Vias to
Topside
PGND
Copper
Vias to
Topside
AGND
Copper
LMZ31506
www.ti.com SNVS993 –JUNE 2013
Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 43 and
Figure 44 show two layers of a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Place a dedicated AGND copper area beneath the LMZ31506.
• Isolate the PH copper area from the VOUT copper area using the AGND copper area.
• Connect the AGND and PGND copper area at one point; see AGND to PGND connection point in Figure 43.
• Place R
SET
, R
RT
, and C
SS
as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
Figure 43. Typical Top-Layer Recommended Figure 44. Typical GND-Layer Recommended
Layout Layout
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