Datasheet

PWRGD
VIN
PVIN
PGND
PH
VOUT
RT/CLK
AGND
VADJ
INH/UVLO
STSEL
SS/TR
VSENSE+
LMZ31503
PWRGD
Logic
+
+
VREF Comp
Power
Stage
and
Control
Logic
Thermal Shutdown
Shutdown
Logic
OCP
VIN
UVLO
OSC w/PLL
LMZ31503
www.ti.com SNVS992 –JULY 2013
ELECTRICAL CHARACTERISTICS (continued)
Over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, V
OUT
= 1.8 V, I
OUT
= 3A,
C
IN1
= 2x 22 µF ceramic, C
IN2
= 68 µF poly-tantalum, C
OUT1
= 4x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Ceramic 22
(4)
C
IN
External input capacitance µF
Non-ceramic 68
(4)
Ceramic 200
(5)
1500
µF
C
OUT
External output capacitance Non-ceramic 5000
Equivalent series resistance (ESR) 35 mΩ
(4) A minimum of 68µF of polymer tantalum and/or ceramic external capacitance is required across the input (VIN and PGND connected)
for proper operation. Locate the capacitor close to the device. See Table 5 for more details. When operating with split VIN and PVIN
rails, place 4.7µF of ceramic capacitance directly at the VIN pin to PGND.
(5) The amount of required output capacitance varies depending on the output voltage (see Table 3 ). The amount of required capacitance
must include ceramic capacitance. Locate the capacitance close to the device. Adding additional capacitance close to the load improves
the response of the regulator to load transients. See Table 3 and Table 5 more details.
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
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