Datasheet

AGND
RT/CLK
R
RT
500 kHz to 2 MHz
External Clock
1 kΩ
470 pF
( )
OUT
IN min
MAX
SW
V
0.75 1
V
CLK _ PW
f
æ ö
ç ÷
´ -
ç ÷
è ø
=
LMZ30606
SNVS995 –JULY 2013 www.ti.com
Synchronization (CLK)
An internal phase locked loop (PLL) has been implemented to allow synchronization between 500 kHz and
2 MHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a
square wave clock signal to the RT/CLK pin with a minimum pulse width of 75 ns. The maximum clock pulse
width must be calculated using Equation 2. The clock signal amplitude must transition lower than 0.4 V and
higher than 2.2 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. Applications
requiring both RT mode and CLK mode, configure the device as shown in Figure 28.
Before the external clock is present, the device works in RT mode and the switching frequency is set by the RT
resistor (R
RT
). When the external clock is present, the CLK mode overrides the RT mode. The device switches
from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the
frequency of the external clock. The device will lock to the external clock frequency approximately 15 µs after a
valid clock signal is present. It is not recommended to switch from CLK mode back to RT mode because the
internal switching frequency drops to a lower frequency before returning to the switching frequency set by the RT
resistor.
(2)
Figure 28. CLK/RT Configuration
Select the synchronization frequency based on the output voltages of the devices being synchronized. Table 7
shows the allowable V
OUT
range for a given switching frequency when operating from a typical 5 V bus and a
typical 3.3 V bus. For the most optimal solution, synchronize to a frequency in the center of the allowable
frequency range. For example, an application requires synchronizing three LMZ30606 devices with output
voltages of 1.2V, 1.8V, and 3.3V, all powered from VIN = 5V. Table 7 shows that all three output voltages can be
synchronized to any frequency between 600 kHz to 1 MHz. For the most optimal solution, choose 800 kHz as the
sychronization frequency. (Values included in the table are based on a resistive load.)
Table 7. Synchronization Frequency vs Output Voltage
VIN = 5V (+/- 10%) VIN = 3.3V (+/- 5%)
SYNCHRONIZATION
R
RT
(kΩ) V
OUT
RANGE (V) V
OUT
RANGE (V)
FREQUENCY (kHz)
MIN MAX MIN MAX
500 open 0.8 1.8 0.8 2.5
550 3400 0.8 2.2 0.8 2.5
600 1800 0.8 3.3 0.8 2.5
650 1200 0.8 3.6 0.8 2.5
700 887 0.8 3.6 0.8 2.5
750 715 0.9 3.6 0.8 2.5
800 590 0.9 3.6 0.8 2.5
850 511 1.0 3.6 0.8 2.5
900 442 1.0 3.6 0.8 2.5
950 392 1.1 3.6 0.8 2.5
1000 348 1.1 3.6 0.8 2.5
1250 232 1.4 3.6 0.9 2.4
1500 174 1.7 3.5 1.1 2.3
1750 137 2.0 3.4 1.3 2.3
2000 113 2.2 3.3 1.4 2.2
18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMZ30606