Datasheet
LMZ30602
SNVS997 –JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
VIN, PWRGD –0.3 7 V
INH/UVLO, RT/CLK –0.3 3.3 V
Input Voltage
SS/TR, STSEL, VADJ –0.3 3 V
SENSE+ VADJ rating must also be met -0.3 VOUT V
PH –0.6 7 V
Output Voltage PH 10ns Transient –2 7 V
VOUT -0.6 VIN V
V
DIFF
(GND to exposed thermal pad) –0.2 0.2 V
RT/CLK, INH/UVLO ±100 µA
Source Current
PH Current Limit A
PH Current Limit A
Sink Current SS/TR ±100 µA
PWRGD 10 mA
Operating Junction Temperature –40 125
(2)
°C
Storage Temperature –65 150 °C
Mechanical Shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 1500
G
Mechanical Vibration Mil-STD-883D, Method 2007.2, 20-2000Hz 20
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the temperature derating curves in the Typical Characteristics section for thermal information.
THERMAL INFORMATION
LMZ30602
THERMAL METRIC
(1)
RKG39 UNIT
39 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
12
ψ
JT
Junction-to-top characterization parameter
(3)
2.2 °C/W
ψ
JB
Junction-to-board characterization parameter
(4)
9.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance, θ
JA
, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with
1 oz. copper and natural convection cooling. Additional airflow reduces θ
JA
.
(3) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature, T
J
, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). T
J
= ψ
JT
* Pdis + T
T
; where Pdis is the power dissipated in the device and T
T
is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature, T
J
, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). T
J
= ψ
JB
* Pdis + T
B
; where Pdis is the power dissipated in the device and T
B
is
the temperature of the board 1mm from the device.
2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LMZ30602