Datasheet

LMZ23610

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SNVS707E –MARCH 2011–REVISED OCTOBER 2013

CURRENT LIMIT

The LMZ23610 is protected by both low side (LS) and high side (HS) current limit circuitry. The LS current limit

detection is carried out during the off-time by monitoring the current through the LS synchronous MOSFET.

Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows

through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 13A (typical) the

current limit comparator disables the start of the next switching period. Switching cycles are prohibited until

current drops below the limit. It should also be noted that d.c. current limit is dependent on duty cycle as

illustrated in the graph in the Typical Performance Characteristics section. The HS current limit monitors the

current of top side MOSFET. Once HS current limit is detected (16A typical) , the HS MOSFET is shutoff

immediately, until the next cycle. Exceeding HS current limit causes V

OUT

to fall. Typical behavior of exceeding

LS current limit is that f

drops to 1/2 of the operating frequency.

THERMAL PROTECTION

The junction temperature of the LMZ23610 should not be allowed to exceed its maximum ratings. Thermal

protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typ) causing the

device to enter a low power standby state. In this state the main MOSFET remains off causing V

OUT

to fall, and

additionally the C

capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for

accidental device overheating. When the junction temperature falls back below 150 °C (typ Hyst = 15°C) the SS

pin is released, V

OUT

rises smoothly, and normal operation resumes.

Applications requiring maximum output current especially those at high input voltage may require additional

derating at elevated temperatures.

PRE-BIASED STARTUP

The LMZ23610 will properly start up into a pre-biased output. This startup situation is common in multiple rail

logic applications where current paths may exist between different power rails during the startup sequence. The

following scope capture shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.8V

pre-bias rising to 3.3V. Trace three is the SS voltage with a C

= 0.47uF. Risetime determined by C

Figure 56. Pre-Biased Startup

Product Folder Links: LMZ23610