Datasheet

ENABLE
2.0M
21 PA
INT-VCC (5V)
1.279V
RUN
12.7k
RENB
42.2k
RENT
VIN
100:
RENH
5.1V
LMZ23605
www.ti.com SNVS659H –MARCH 2011–REVISED OCTOBER 2013
The LMZ23605 typical application shows 12.7kΩ for R
ENB
and 42.2kΩ for R
ENT
resulting in a rising UVLO of
5.46V. Note that this divider presents 8.33V to the input when the divider is raised to 36V which would exceed
the recommended 5.5V limit for Enable. A midpoint 5.1V Zener clamp is applied to allow the application to cover
the full 6V to 36V range of operation. The zener clamp is not required if the target application prohibits the
maximum Enable input voltage from being exceeded.
Additional enable voltage hysteresis can be added with the inclusion of R
ENH
. It is possible to select values for
R
ENT
and R
ENB
such that R
ENH
is a value of zero allowing it to be omitted from the design.
Rising threshold can be calculated as follows:
V
EN
(rising) = 1.279 ( 1 + (R
ENT
|| 2 meg)/ R
ENB
) (2)
Whereas the falling threshold level can be calculated using:
V
EN
(falling) = V
EN
(rising) – 21 µA ( R
ENT
|| 2 meg || R
ENTB
+ R
ENH
) (3)
Figure 48. Enable input detail
OUTPUT VOLTAGE SELECTION
Output voltage is determined by a divider of two resistors connected between V
O
and ground. The midpoint of
the divider is connected to the FB input.
The regulated output voltage determined by the external divider resistors R
FBT
and R
FBB
is:
V
O
= 0.796V * (1 + R
FBT
/ R
FBB
) (4)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
R
FBT
/ R
FBB
= (V
O
/ 0.796V) - 1 (5)
These resistors should generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.
For V
O
= 0.8V the FB pin can be connected to the output directly and R
FBB
can be set to 8.06kΩ to provide
minimum output load.
A table of values for R
FBT
, and R
FBB
, is included in the simplified applications schematic on page 2.
SOFT-START CAPACITOR SELECTION
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.
Upon turn-on, after all UVLO conditions have been passed, an internal 1.6mSec circuit slowly ramps the SS/TRK
input to implement internal soft start. If 2 mSec is an adequate turn–on time then the Css capacitor can be left
unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.
Soft start duration is given by the formula:
t
SS
= V
REF
* C
SS
/ Iss = 0.796V * C
SS
/ 50uA (6)
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