Datasheet

VIN
PGND
V
IN
V
OUT
C
IN
C
OUT
Loop 1
Loop 2
VOUT
High
di/dt
T
JA
<
T
J-MAX
± T
A-MAX
P
IC_LOSS
T
JA
<
(125 - 50) °C
5.3 W
< 14.15
°C
W
500
T
CA
Board Area_cm
2
8
°C x cm
2
W
.
LMZ22010
www.ti.com SNVS687G –MARCH 2011–REVISED OCTOBER 2013
To reach θ
CA
= 13.15, the PCB is required to dissipate heat effectively. With no airflow and no external heat-sink,
a good estimate of the required board area covered by 2 oz. copper on both the top and bottom metal layers is:
(15)
As a result, approximately 38.02 square cm of 2 oz copper on top and bottom layers is the minimum required
area for the example PCB design. This is 6.16 x 6.16 cm (2.42 x 2.42 in) square. The PCB copper heat sink
must be connected to the exposed pad. For best performance, use approximately 100, 8mil thermal vias spaced
59 mil (1.5 mm) apart connect the top copper to the bottom copper.
Another way to estimate the temperature rise of a design is using θ
JA
. An estimate of θ
JA
for varying heat sinking
copper areas and airflows can be found in the typical applications curves. If our design required the same
operating conditions as before but had 225 LFPM of airflow. We locate the required θ
JA
of
(16)
On the Theta JA vs copper heatsinking curve, the copper area required for this application is now only 2 square
inches. The airflow reduced the required heat sinking area by a factor of three.
To reduce the heat sinking copper area further, this package is compatable with D3-PAK surface mount heat
sinks.
For an example of a high thermal performance PCB layout for SIMPLE SWITCHER© power modules, refer to
AN-2093 SNVA460, AN-2084 SNVA456, AN-2125 SNVA473, AN-2020 SNVA419 and AN-2026 SNVA424.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules. A good layout example is shown in
Figure 59.
Figure 52. High Current Loops
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout as
shown in the figure above. The high current loops that do not overlap have high di/dt content that will cause
observable high frequency noise on the output pin if the input capacitor (C
IN
) is placed at a distance away from
the LMZ22010. Therefore place C
IN
as close as possible to the LMZ22010 VIN and PGND exposed pad. This will
minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output
capacitor should consist of a localized top side plane that connects to the PGND exposed pad (EP).
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