Datasheet

9A
C
OUT
t
(0.165V - 9A x 0.003) x ( )
350e3
3.3V
t
615 PF
I
step
C
OUT
t
('V
OUT
- I
STEP
x ESR) x (
)
f
SW
V
OUT
1.07k
Rfbb
2.26k
Rfbt
107
Rtkb
226
Rtkt
SS
3.3V Master
FB
2.5Vout
50 PA
Int VCC
LMZ22010
www.ti.com SNVS687G –MARCH 2011–REVISED OCTOBER 2013
TRACKING SUPPLY DIVIDER OPTION
The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the
3.3V system rail) where the slave module output voltage is lower than that of the master. Proper configuration
allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails
during ramp-up is small (i.e. <0.15V typ). The values for the tracking resistive divider should be selected such
that the effect of the internal 50uA current source is minimized. In most cases the ratio of the tracking divider
resistors is the same as the ratio of the output voltage setting divider. Proper operation in tracking mode dictates
the soft-start time of the slave rail be shorter than the master rail; a condition that is easy to satisfy since the C
SS
cap is replaced by R
TKB
. The tracking function is only supported for the power up interval of the master supply;
once the SS/TRK rises past 0.795V the input is no longer enabled and the 50 uA internal current source is
switched off.
Figure 51. Tracking option input detail
C
OUT
SELECTION
None of the required C
OUT
output capacitance is contained within the module. A minimum value ranging from 330
μF for 6V
OUT
to 660 μF for 1.2V
OUT
applications is required based on the values of internal compensation in the
error amplifier. These minimum values can be decreased if the effective capacitor ESR is higher than 15
mOhms.
A Low ESR (15 mOhm) tantalum, organic semiconductor or specialty polymer capacitor types in parallel with a
47nF X7R ceramic capacitor for high frequency noise reduction is recommended for obtaining lowest ripple. The
output capacitor C
OUT
may consist of several capacitors in parallel placed in close proximity to the module. The
output voltage ripple of the module depends on the equivalent series resistance (ESR) of the capacitor bank, and
can be calculated by multiplying the ripple current of the module by the effective impedance of your chosen
output capacitors (for ripple current calculation, see Equation 18). Electrolytic capacitors will have large ESR and
lead to larger output ripple than ceramic or polymer types. For this reason a combination of ceramic and polymer
capacitors is recommended for low output ripple performance.
The output capacitor assembly must also meet the worst case ripple current rating of Δi
L
, as calculated in
Equation 18 below. Loop response verification is also valuable to confirm closed loop behavior.
For applications with dynamic load steps; the following equation provides a good first pass approximation of C
OUT
for load transient requirements.
(8)
For 12V
IN
, 3.3V
OUT
, a transient voltage of 5% of V
OUT
= 0.165V (ΔV
OUT
), a 9A load step (I
STEP
), an output
capacitor effective ESR of 3 mOhms, and a switching frequency of 350kHz (f
SW
):
(9)
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