Datasheet

ENABLE
2.0M
13 PA
INT-VCC (5V)
1.274V
RUN
12.7k
RENB
42.2k
RENT
VIN
100:
RENH
5.1V
LMZ22010
SNVS687G –MARCH 2011–REVISED OCTOBER 2013 www.ti.com
Figure 50. Enable input detail
OUTPUT VOLTAGE SELECTION
Output voltage is determined by a divider of two resistors connected between V
OUT
and AGND. The midpoint of
the divider is connected to the FB input.
The regulated output voltage determined by the external divider resistors R
FBT
and R
FBB
is:
V
OUT
= 0.795V * (1 + R
FBT
/ R
FBB
) (4)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
R
FBT
/ R
FBB
= (V
OUT
/ 0.795V) - 1 (5)
These resistors should generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.
For V
OUT
= 0.8V the FB pin can be connected to the output directly and R
FBB
can be set to 8.06kΩ to provide
minimum output load.
A table of values for R
FBT
, and R
FBB
, is included in the Simplified Application Schematic.
SOFT-START CAPACITOR SELECTION
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.
Upon turn-on, after all UVLO conditions have been passed, an internal 1.6msec circuit slowly ramps the SS input
to implement internal soft start. If 1.6 msec is an adequate turn–on time then the Css capacitor can be left
unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.
Soft start duration is given by the formula:
t
SS
= V
REF
* C
SS
/ Iss = 0.795V * C
SS
/ 50uA (6)
This equation can be rearranged as follows:
C
SS
= t
SS
* 50μA / 0.795V (7)
Using a 0.22μF capacitor results in 3.5 msec typical soft-start duration; and 0.47μF results in 7.5 msec typical.
0.47 μF is a recommended initial value.
As the soft-start input exceeds 0.795V the output of the power stage will be in regulation and the 50 μA current is
deactivated. Note that the following conditions will reset the soft-start capacitor by discharging the SS input to
ground with an internal current sink.
• The Enable input being pulled low
• A thermal shutdown condition
• V
IN
falling below 4.3V (TYP) and triggering the V
CC
UVLO
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