Datasheet

LMZ22005
www.ti.com SNVS686I –MARCH 2011–REVISED OCTOBER 2013
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout as
shown in Figure 48 above. The high current loops that do not overlap have high di/dt content that will cause
observable high frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away from
the LMZ22005. Therefore place C
IN1
as close as possible to the LMZ22005 VIN and PGND exposed pad. This
will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output
capacitor should consist of a localized top side plane that connects to the PGND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the AGND pin
of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.
Additionally provide the single point ground connection from pin 4 (AGND) to EP/PGND.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
FBT
and R
FBB
, and the feed forward capacitor C
FF
, should be located close to the FB
pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from R
FBT
,
R
FBB
, and C
FF
should be routed away from the body of the LMZ22005 to minimize possible noise pickup.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so
will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If
the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner
layer heat-spreading ground planes. For best results use a 6 x 10 via array with minimum via diameter of 8mils
thermal vias spaced 39mils (1.0 mm). Ensure enough copper area is used for heat-sinking to keep the junction
temperature below 125°C.
Additional Features
SYNCHRONIZATION INPUT
The PWM switching frequency can be synchronized to an external frequency source. If this feature is not used,
connect this input either directly to ground, or connect to ground through a resistor of 1.5 kΩ ohm or less. The
allowed synchronization frequency range is 650kHz to 950 kHz. The typical input threshold is 1.4V transition
level. Ideally the input clock should overdrive the threshold by a factor of 2, so direct drive from 3.3V logic via a
1.5kΩ Thevenin source resistance is recommended. Note that applying a sustained “logic 1” corresponds to zero
Hz PWM frequency and will cause the module to stop switching.
OUTPUT OVER-VOLTAGE PROTECTION
If the voltage at FB is greater than the 0.86V internal reference the output of the error amplifier is pulled toward
ground causing V
O
to fall.
CURRENT LIMIT
The LMZ22005 is protected by both low side (LS) and high side (HS) current limit circuitry. The LS current limit
detection is carried out during the off-time by monitoring the current through the LS synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 5.4A (typical) the
current limit comparator disables the start of the next switching period. Switching cycles are prohibited until
current drops below the limit. It should also be noted that d.c. current limit is dependent on duty cycle as
illustrated in the graph in the typical performance section. The HS current limit monitors the current of top side
MOSFET. Once HS current limit is detected (7A typical) , the HS MOSFET is shutoff immediately, until the next
cycle. Exceeding HS current limit causes V
O
to fall. Typical behavior of exceeding LS current limit is that f
SW
drops to 1/2 of the operating frequency.
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