Datasheet

VIN
GND
V
IN
V
O
C
in1
C
O1
Loop 1
Loop 2
LMZ22003
VOUT
High
di/dt
LMZ22003
www.ti.com SNVS658H –MARCH 2011–REVISED OCTOBER 2013
Figure 48. PC Board Layout
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout as
shown in Figure 48. The high current loops that do not overlap have high di/dt content that will cause observable
high frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away from the
LMZ22003. Therefore place C
IN1
as close as possible to the LMZ22003 VIN and PGND exposed pad. This will
minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output
capacitor should consist of a localized top side plane that connects to the PGND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the AGND pin
of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.
Additionally provide the single point ground connection from pin 4 (AGND) to EP/PGND.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
FBT
and R
FBB
should be located close to the FB pin. Since the FB node is high
impedance, maintain the copper area as small as possible. The traces from R
FBT
, R
FBB
should be routed away
from the body of the LMZ22003 to minimize possible noise pickup.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so
will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If
the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner
layer heat-spreading ground planes. For best results use a 6 x 10 via array with minimum via diameter of 8mils
thermal vias spaced 39mils (1.0 mm). Ensure enough copper area is used for heat-sinking to keep the junction
temperature below 125°C.
Additional Features
SYNCHRONIZATION INPUT
The PWM switching frequency can be synchronized to an external frequency source. If this feature is not used,
connect this input either directly to ground, or connect to ground through a resistor of 1.5 kΩ ohm or less. The
allowed synchronization frequency range is 650kHz to 950 kHz. The typical input threshold is 1.4V transition
level. Ideally the input clock should overdrive the threshold by a factor of 2, so direct drive from 3.3V logic via a
1.5kΩ Thevenin source resistance is recommended. Note that applying a sustained “logic 1” corresponds to zero
Hz PWM frequency and will cause the module to stop switching.
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