Datasheet

LMZ22003
SNVS658H –MARCH 2011–REVISED OCTOBER 2013 www.ti.com
(As a point of reference, the worst case ripple current will occur when the module is presented with full load
current and when V
IN
= 2 * V
O
).
Recommended minimum input capacitance is 22uF X7R (or X5R) ceramic with a voltage rating at least 25%
higher than the maximum applied input voltage for the application. It is also recommended that attention be paid
to the voltage and temperature derating of the capacitor selected. It should be noted that ripple current rating of
ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor
manufacturer for this parameter.
If the system design requires a certain minimum value of peak-to-peak input ripple voltage (ΔV
IN
) be maintained
then the following equation may be used.
C
IN
≥ I
O
* D * (1–D) / f
SW-CCM
* ΔV
IN
(9)
If ΔV
IN
is 1% of V
IN
for a 12V input to 3.3V output application this equals 120 mV and f
SW
= 812 kHz.
C
IN
≥ 3A * 3.3V/12V * (1– 3.3V/12V) / (812000 * 0.120 V)
≥ 6.14μF
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines. The LMZ22003 typical applications schematic
and evaluation board include a 150 μF 50V aluminum capacitor for this function. There are many situations
where this capacitor is not necessary.
POWER DISSIPATION AND BOARD THERMAL REQUIREMENTS
When calculating module dissipation use the maximum input voltage and the average output current for the
application. Many common operating conditions are provided in the characteristic curves such that less common
applications can be derived through interpolation. In all designs, the junction temperature must be kept below the
rated maximum of 125°C.
For the design case of V
IN
= 12V, V
O
= 3.3V, I
O
= 3A, and T
AMB(MAX)
= 85°C, the module must see a thermal
resistance from case to ambient of less than:
θ
CA
< (T
J-MAX
– T
A-MAX
) / P
IC-LOSS
- θ
JC
(10)
Given the typical thermal resistance from junction to case to be 1.9 °C/W. Use the 85°C power dissipation curves
in the Typical Performance Characteristics section to estimate the P
IC-LOSS
for the application being designed. In
this application it is 2W.
θ
CA
= (125 – 85) / 2W – 1.9 = 18.1 (11)
To reach θ
CA
= 18.1, the PCB is required to dissipate heat effectively. With no airflow and no external heat-sink,
a good estimate of the required board area covered by 2 oz. copper on both the top and bottom metal layers is:
Board_Area_cm
2
= 500°C x cm
2
/W / θ
CA
(12)
As a result, approximately 28 square cm of 2 oz copper on top and bottom layers is required for the PCB design.
The PCB copper heat sink must be connected to the exposed pad. Approximately sixty, 8mil thermal vias spaced
39 mils (1.0 mm) apart connect the top copper to the bottom copper. For an example of a high thermal
performance PCB layout for SIMPLE SWITCHER© power modules, refer to AN-2085, AN-2125, AN-2020 and
AN-2026.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules. A good example layout is shown in
Figure 52.
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