Datasheet

LMZ14203H
SNVS692D –JANUARY 2011–REVISED OCTOBER 2013 www.ti.com
A table of values for R
FBT
, R
FBB
, and R
ON
is included in the simplified applications schematic (see Figure 5).
SOFT-START CAPACITOR, C
SS
, SELECTION
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
Upon turn-on, after all UVLO conditions have been passed, an internal 8uA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula:
t
SS
= V
REF
x C
SS
/ Iss = 0.8V x C
SS
/ 8uA (4)
Equation 4 can be rearranged as follows:
C
SS
= t
SS
x 8 μA / 0.8V (5)
Use of a 4700pF capacitor results in 0.5ms soft-start duration. This is a recommended value. Note that high
values of C
SS
capacitance will cause more output voltage droop when a load transient goes across the DCM-
CCM boundary. Use Equation 22 to find the DCM-CCM boundary load current for the specific operating
condition. If a fast load transient response is desired for steps between DCM and CCM mode the softstart
capacitor value should be less than 0.018µF.
Note that the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an
internal 200 μA current sink:
• The enable input being “pulled low”
• Thermal shutdown condition
• Over-current fault
• Internal V
IN
UVLO
OUTPUT CAPACITOR, C
O
, SELECTION
None of the required output capacitance is contained within the module. At a minimum, the output capacitor must
meet the worst case RMS current rating of 0.5 x I
LR P-P
, as calculated in Equation 23. Beyond that, additional
capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is
generally required. Experimentation will be required if attempting to operate with a minimum value. Low ESR
capacitors, such as ceramic and polymer electrolytic capacitors are recommended.
CAPACITANCE
Equation 6 provides a good first pass approximation of C
O
for load transient requirements:
C
O
≥I
STEP
x V
FB
x L x V
IN
/ (4 x V
O
x (V
IN
— V
O
) x V
OUT-TRAN
) (6)
As an example, for 3A load step, V
IN
= 24V, V
OUT
= 12V, V
OUT-TRAN
= 50mV:
C
O
≥ 3A x 0.8V x 10μH x 24V / (4 x 12V x ( 24V — 12V) x 50mV) (7)
C
O
≥ 20μF (8)
ESR
The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger V
OUT
peak-to-
peak ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the over-
voltage protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired V
OUT
peak-to-peak ripple voltage and to avoid over-voltage protection during normal operation. The following
equations can be used:
ESR
MAX-RIPPLE
≤ V
OUT-RIPPLE
/ I
LR P-P
(9)
where I
LR P-P
is calculated using Equation 23.
ESR
MAX-OVP
< (V
FB-OVP
- V
FB
) / (I
LR P-P
x A
FB
) (10)
where A
FB
is the gain of the feedback network from V
OUT
to V
FB
at the switching frequency.
As worst case, assume the gain of A
FB
with the C
FF
capacitor at the switching frequency is 1.
The selected capacitor should have sufficient voltage and RMS current rating. The RMS current through the
output capacitor is:
I(C
OUT(RMS)
) = I
LR P-P
/ √12 (11)
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