Datasheet

LMZ14202H

www.ti.com

SNVS691E –JANUARY 2011–REVISED OCTOBER 2013

CURRENT LIMIT

Current limit detection is carried out during the off-time by monitoring the current in the synchronous MOSFET.

Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows

through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds I

the current

limit comparator disables the start of the next on-time period. The next switching cycle will occur only if the FB

input is less than 0.8V and the inductor current has decreased below I

. Inductor current is monitored during the

period of time the synchronous MOSFET is conducting. So long as inductor current exceeds I

, further on-time

intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due to the longer

off-time. It should also be noted that DC current limit varies with duty cycle, switching frequency, and

temperature.

THERMAL PROTECTION

The junction temperature of the LMZ14202H should not be allowed to exceed its maximum ratings. Thermal

protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typ) causing the

device to enter a low power standby state. In this state the main MOSFET remains off causing V

to fall, and

additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for

accidental device overheating. When the junction temperature falls back below 145 °C (typ Hyst = 20 °C) the SS

pin is released, V

rises smoothly, and normal operation resumes.

ZERO COIL CURRENT DETECTION

The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which

inhibits the synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables the

DCM operating mode, which improves efficiency at light loads.

PRE-BIASED STARTUP

The LMZ14202H will properly start up into a pre-biased output. This is startup situation is common in multiple rail

logic applications where current paths may exist between different power rails during the startup sequence. The

pre-bias level of the output voltage must be less than the input UVLO set point. This will prevent the output pre-

bias from enabling the regulator through the high side MOSFET body diode.

Power Module SMT Guidelines

The recommendations below are for a standard module surface mount assembly

• Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads

• Stencil Aperture

– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land

pattern

– For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation

• Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher

• Stencil Thickness – 0.125 to 0.15mm

• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density

• Maximum number of reflows allowed is one

Product Folder Links: LMZ14202H