Datasheet

VIN
GND
V
IN
V
O
C
in1
C
O1
Loop 1
Loop 2
LMZ14201
VOUT
High
di/dt
LMZ14201
SNVS649F –JANUARY 2010–REVISED OCTOBER 2013 www.ti.com
As a result, approximately 6 square cm of 1 oz copper on top and bottom layers is required for the PCB design.
Additional area will decrease die temperature proportionately. The PCB copper heat sink must be connected to
the exposed pad. Approximately thirty six, 8mils thermal vias spaced 59mils (1.5 mm) apart must connect the top
copper to the bottom copper. For an example of a high thermal performance PCB layout of approximately 31
square cm area. Refer to the Evaluation Board application note AN-2024 SNVA422. For more information on
thermal design see AN-2020 SNVA419 and AN-2026 SNVA424.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout. The
high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on
the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14201. Therefore place C
IN1
as close as possible to the LMZ14201 VIN and GND exposed pad. This will minimize the high di/dt area and
reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized
top side plane that connects to the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of
the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly
handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide
the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
FBT
and R
FBB
, and the feed forward capacitor C
FF
, should be located close to the FB
pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from
R
FBT
, R
FBB
, and C
FF
should be routed away from the body of the LMZ14201 to minimize noise.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so
will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If
the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner
layer heat-spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 8mils
thermal vias spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction
temperature below 125°C.
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