Datasheet

LMZ12010
SNVS667G –FEBRUARY 2010–REVISED OCTOBER 2013 www.ti.com
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the AGND pin
of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.
Additionally provide a single point ground connection from pin 4 (AGND) to EP/PGND.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
FBT
and R
FBB
should be located close to the FB pin. Since the FB node is high
impedance, maintain the copper area as small as possible. The traces from R
FBT
, R
FBB
should be routed away
from the body of the LMZ12010 to minimize possible noise pickup.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so
will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If
the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading
ground planes. For best results use a 10 x 10 via array or larger with a minimum via diameter of 8mil thermal
vias spaced 46.8mil (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction
temperature below 125°C.
Additional Features
OUTPUT OVER-VOLTAGE PROTECTION
If the voltage at FB is greater than a 0.86V internal reference, the output of the error amplifier is pulled toward
ground, causing V
OUT
to fall.
CURRENT LIMIT
The LMZ12010 is protected by both low side (LS) and high side (HS) current limit circuitry. The LS current limit
detection is carried out during the off-time by monitoring the current through the LS synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 13A (typical) the
current limit comparator disables the start of the next switching period. Switching cycles are prohibited until
current drops below the limit. It should also be noted that d.c. current limit is dependent on duty cycle as
illustrated in the graph in the Typical Performance Characteristics section. The HS current limit monitors the
current of top side MOSFET. Once HS current limit is detected (16A typical) , the HS MOSFET is shutoff
immediately, until the next cycle. Exceeding HS current limit causes V
OUT
to fall. Typical behavior of exceeding
LS current limit is that f
SW
drops to 1/2 of the operating frequency.
THERMAL PROTECTION
The junction temperature of the LMZ12010 should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typ) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing V
OUT
to fall, and
additionally the C
SS
capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 150 °C (typ Hyst = 15°C) the SS
pin is released, V
OUT
rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require additional
derating at elevated temperatures.
PRE-BIASED STARTUP
The LMZ12010 will properly start up into a pre-biased output. This startup situation is common in multiple rail
logic applications where current paths may exist between different power rails during the startup sequence. The
following scope capture shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.8V
pre-bias rising to 3.3V. Trace three is the SS voltage with a C
SS
= 0.47uF. Risetime determined by C
SS
.
20 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: LMZ12010