Datasheet

C
SS
R
FBB
SS FB
EN
PGND
V
OUT
AGND
VIN
VOUT
LMZ Module
C
O
3,4
C
O
1
(OPT)
C
O
2
(OPT)
C
O
5
(OPT)
R
ENB
R
ENT
D1
5.1V
(OPT)
C
FF
R
FBT_3.3
R
FBT_3.3b
VOUT SELECT
(J1)
5Vout
3.3Vout
2.5Vout
1.2Vout
R
FB_LP
TEMP
SENSE
R
TS
R
FBT_5
R
FBT_5b
R
FBT_1.2
R
FBT_1.2b
R
FBT_2.5
R
FBT_2.5b
C
IN
1
V
IN
C
IN
6
C
IN
5
+
C
IN
2,3,4
L1
Test Connections www.ti.com
Figure 1. Simplified Schematic
3 Test Connections
The board should be connected to a power supply and load as shown below in Figure 2. The EN post is
connected to the UVLO circuit on the back of the board. There is a resistive divider implemented on the
board that can be used to establish a precision UVLO level for the board that is currently set to 5.7V. A
common user change to this circuit is to adjust the value of RENT and RENB to adjust the operating
UVLO to that of the target application. for calculations, see the device-specific data sheet. Note that if in
the end application the EN pin voltage does not exceed 5.5V at maximum Vin, then the enable clamp
zener D1 can be omitted. (On revision A of the board the overlay for the zener diode has the cathode and
anode incorrectly labeled). Pull EN low to shutdown the module.
2
AN-2134 LMZ13610/8/6 and LMZ12010/8/6 Evaluation Board SNVA478C–April 2011–Revised April 2013
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