Datasheet

LMZ12003EXT
www.ti.com SNVS663G –JUNE 2010–REVISED OCTOBER 2013
3. Minimize trace length to the FB pin.
Both feedback resistors, R
FBT
and R
FBB
, and the feed forward capacitor C
FF
, should be located close to the FB
pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from
R
FBT
, R
FBB
, and C
FF
should be routed away from the body of the LMZ12003EXT to minimize noise.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so
will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If
the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner
layer heat-spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 8mils
thermal vias spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction
temperature below 125°C.
Additional Features
OUTPUT OVER-VOLTAGE COMPARATOR
The voltage at FB is compared to a 0.92V internal reference. If FB rises above 0.92V the on-time is immediately
terminated. This condition is known as over-voltage protection (OVP). It can occur if the input voltage is
increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top
MOSFET on-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain
on until inductor current falls to zero.
CURRENT LIMIT
Current limit detection is carried out during the off-time by monitoring the current in the synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 4.2A (typical) the
current limit comparator disables the start of the next on-time period. The next switching cycle will occur only if
the FB input is less than 0.8V and the inductor current has decreased below 4.2A. Inductor current is monitored
during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds 4.2A,
further on-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due
to the longer off-time. It should also be noted that current limit is dependent on both duty cycle and temperature
as illustrated in the graphs in the typical performance section.
THERMAL PROTECTION
The junction temperature of the LMZ12003EXT should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typ) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing V
O
to fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 145 °C (typ Hyst = 20 °C) the SS
pin is released, V
O
rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require application
derating at elevated temperatures.
ZERO COIL CURRENT DETECTION
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which
inhibits the synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables the
DCM operating mode, which improves efficiency at light loads.
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