Datasheet

LMZ12003EXT
www.ti.com SNVS663G –JUNE 2010–REVISED OCTOBER 2013
The LMZ12003EXT demonstration and evaluation boards use 11.8kΩ for R
ENB
and 32.4kΩ for R
ENT
resulting in a
rising UVLO of 4.5V. This divider presents 5.34V to the EN input when the divider input is raised to 20V.
OUTPUT VOLTAGE SELECTION
Output voltage is determined by a divider of two resistors connected between V
O
and ground. The midpoint of
the divider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal
operation an on-time cycle is initiated when the voltage on the FB pin falls below 0.8V. The main MOSFET on-
time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8V. As long as the voltage at
FB is above 0.8V, on-time cycles will not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
V
O
= 0.8V * (1 + R
FBT
/ R
FBB
) (2)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
R
FBT
/ R
FBB
= (V
O
/ 0.8V) - 1
These resistors should be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.
For V
O
= 0.8V the FB pin can be connected to the output directly so long as an output preload resistor remains
that draws more than 20uA. Converter operation requires this minimum load to create a small inductor ripple
current and maintain proper regulation when no load is present.
A feed-forward capacitor is placed in parallel with R
FBT
to improve load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple.
A table of values for R
FBT
, R
FBB
, C
FF
and R
ON
is included in the applications schematic.
SOFT-START CAPACITOR SELECTION
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
Upon turn-on, after all UVLO conditions have been passed, an internal 8uA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula:
t
SS
= V
REF
* C
SS
/ Iss = 0.8V * C
SS
/ 8uA (3)
This equation can be rearranged as follows:
C
SS
= t
SS
* 8 μA / 0.8V
Use of a 0.022μF capacitor results in 2.2 msec soft-start duration. This is recommended as a minimum value.
As the soft-start input exceeds 0.8V the output of the power stage will be in regulation. The soft-start capacitor
continues charging until it reaches approximately 3.8V on the SS pin. Voltage levels between 0.8V and 3.8V
have no effect on other circuit operation. Note that the following conditions will reset the soft-start capacitor by
discharging the SS input to ground with an internal 200 μA current sink.
• The enable input being “pulled low ”
• Thermal shutdown condition
• Over-current fault
• Internal Vcc UVLO (Approx 4V input to V
IN
)
C
O
SELECTION
None of the required C
O
output capacitance is contained within the module. At a minimum, the output capacitor
must meet the worst case minimum ripple current rating of 0.5 * I
LR P-P
, as calculated in Equation 14 below.
Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A
minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with a
minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 SNVA422 for more
detail.
The following equation provides a good first pass approximation of C
O
for load transient requirements:
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