Datasheet

I
step
x V
FB
x L x V
IN
4 x V
OUT
x (V
IN
-V
OUT
) x 'Vo_tran
C
o
t
'i
L
=
(5V ± 2.5V) x
1.5 PH x 1 MHz
2.5V
5V
= 833 mA
'i
L
=
(V
IN
- V
OUT
) x D
L x f
SW
'C
OUT
=
'i
L
8 x f
SW
x ['V
OUT
± ('i
L
x R
ESR
)]
I
Cin(RMS)
= I
OUT
x
D(1-D)
C
in
8
5A x ( ) x (1 - )
1 MHz x 50mV
2.5V
5V
2.5V
5V
8 25µF
D =
V
OUT
V
IN
LMZ10505EXT
SNVS669G –JUNE 2010–REVISED OCTOBER 2013 www.ti.com
where the PWM duty cycle, D, is given by:
(2)
If ΔV
IN
is 1% of V
IN
, this equals to 50 mV and f
SW
= 1 MHz
(3)
A second criteria before finalizing the C
in
bypass capacitor is the RMS current capability. The necessary RMS
current rating of the input capacitor to a buck regulator can be estimated by
(4)
(5)
With this high AC current present in the input capacitor, the RMS current rating becomes an important
parameter. The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. Select an
input capacitor rated for at least the maximum calculated I
Cin(RMS)
.
Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input
capacitance and parasitic inductance.
Output Capacitor Selection
In general, 22 µF to 100 µF high quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum
output voltage is sufficient given the optimal high frequency characteristics and low ESR of ceramic dielectrics.
Although, the output capacitor can also be of electrolytic chemistry for increased capacitance density.
Two output capacitance equations are required to determine the minimum output capacitance. One equation
determines the output capacitance (C
O
) based on PWM ripple voltage. The second equation determines C
O
based on the load transient characteristics. Select the largest capacitance value of the two.
The minimum capacitance, given the maximum output voltage ripple (ΔV
OUT
) requirement, is determined by the
following equation:
(6)
Where the peak to peak inductor current ripple (Δi
L
) is equal to:
(7)
R
ESR
is the total output capacitor ESR, L is the inductance value of the internal power inductor, where L = 1.5
µH, and f
SW
= 1 MHz. Therefore, per the design example:
(8)
The minimum output capacitance requirement due to the PWM ripple voltage is:
(9)
(10)
Three miliohms is a typical R
ESR
value for ceramic capacitors.
The following equation provides a good first pass capacitance requirement for a load transient:
(11)
Where I
step
is the peak to peak load step (10% to 90% of the maximum load for this example), V
FB
= 0.8V, and
ΔV
o_tran
is the maximum output voltage deviation, which is ±20 mV.
Therefore the capacitance requirement for the given design parameters is:
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