Datasheet

VIN
EN
GND
LMZ10503EXT
R
enb
R
ent
V
IN
Cin1
V
IN(UVLO)
= 1.23V x
R
ent
+ R
enb
R
enb
LMZ10503EXT
www.ti.com SNVS668G –JUNE 2010–REVISED OCTOBER 2013
3. Minimize trace length to the FB pin.
Both feedback resistors, R
fbt
and R
fbb
, and the compensation components, R
comp
and C
comp
, should be located
close to the FB pin. Since the FB node is high impedance, keep the copper area as small as possible. This is
most important as relatively high value resistors are used to set the output voltage.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made at the load. Doing so
will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If
the PCB has multiple copper layers, thermal vias can also be employed to make connection to inner layer heat-
spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 8mils thermal vias
spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature
below 125°C.
Additional Features
Enable
The LMZ10503EXT features an enable (EN) pin and associated comparator to allow the user to easily sequence
the LMZ10503EXT from an external voltage rail, or to manually set the input UVLO threshold. The turn-on or
rising threshold and hysteresis for this comparator are typically 1.23V and 0.15V respectively. The precise
reference for the enable comparator allows the user to ensure that the LMZ10503EXT will be disabled when the
system demands it to be.
The EN pin should not be left floating. For always-on operation, connect EN to VIN.
Enable AND UVLO
Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the
part begins switching can be increased above the normal input UVLO level according to
(19)
For example, suppose that the required input UVLO level is 3.69V. Choosing R
enb
= 10 kΩ, then we calculate
R
ent
= 20 kΩ.
Alternatively, the EN pin can be driven from another voltage source to cater to system sequencing requirements
commonly found in FPGA and other multi-rail applications. The following schematic shows an LMZ10503EXT
that is sequenced to start based on the voltage level of a master system rail (V
OUT1
).
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