Datasheet
VIN
GND
V
IN
V
OUT
C
in1
C
O1
Loop 1
Loop 2
LMZ10503EXT
VOUT
dI
dt
High
500
T
CA
Board Area_cm
2
8
°C x cm
2
W
.
LMZ10503EXT
SNVS668G –JUNE 2010–REVISED OCTOBER 2013
www.ti.com
Given the typical thermal resistance from junction to case (θ
JC
) to be 1.9°C/W (typ.). Continuously operating at a
T
J
greater than 125°C will have a shorten life span.
To reach θ
CA
= 69.5°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat,
a good estimate of the required board area covered by 1oz. copper on both the top and bottom metal layers is:
(17)
(18)
As a result, approximately 7.2 square cm of 1oz. copper on top and bottom layers is required for the PCB design.
The PCB copper heat sink must be connected to the exposed pad (EP). Approximately thirty six, 8mils thermal
vias spaced 59mils (1.5 mm) apart must connect the top copper to the bottom copper. For an extended
discussion and formulations of thermal rules of thumb, refer to AN-2020 (SNVA419). For an example of a high
thermal performance PCB layout with θ
JA
of 20°C/W, refer to the evaluation board application note AN-2074
(SNVA450) and for results of a study of the effects of the PCB designs, refer to AN-2026 (SNVA424).
PC Board Layout Guidelines
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
Figure 20. High Current Loops
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths. The high current that
does not overlap contains high di/dt, see Figure 20. Therefore physically place input capacitor (C
in1
) as close as
possible to the LMZ10503EXT VIN pin and GND exposed pad to avoid observable high frequency noise on the
output pin. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the
input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad
(EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed only to the GND
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly placed, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.
Provide the single point ground connection from pin 4 to EP.
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