Datasheet

LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013 www.ti.com
4. Design the Loop Filter
5. Determine the Modulator Order
6. Determine Dithering and Potential Larger Equivalent Fractional Value
External VCO Mode
The LMX2541 also has provisions to be driven with an external VCO as well. In this mode, the user has the
option of using the RFout pin output, although if this pin is used, the VCO input frequency is restricted to 4 GHz.
If not used, the RFout pin should be left open. The VCO input is connected to the ExtVCOin pin. Because the
internal VCO is not being used, the part option that is being used does not have a large impact on phase noise
or spur performance. It is also possible to switch between both Full Chip mode and External VCO mode.
Internal VCO Digital Calibration Time
When the LMX2541 is used in full chip mode, the integrated VCO can impact the lock time of the system. This
digital calibration chooses the closest VCO frequency band, which typically gets the device within a frequency
error 10 MHz or less of the final settling frequency, although this final frequency error can change slightly
between the different options of the LMX2541. Once this digital calibration is finished, this remaining frequency
error must settle out, and this remaining lock time is dictated by the loop bandwidth.
Based on measured data, this digital calibration time can be approximated by the following formula:
LockTime = A + B/CLK + C·ΔF + D·( ΔF/CLK ) (9)
Symbo1 Value Units
Locktime Varies µs
A 30 μs
B 3800 None
C 0.1 us/MHz
D 2 µs
ΔF Varies MHz
f
OSCin
/ 2
for 0 ≤ OSC_FREQ ≤ 63
f
OSCin
/ 4
CLK None
for 64 ≤ OSC_FREQ ≤ 127
f
OSCin
/ 8
for 128 ≤ OSC_FREQ
For example, consider the LMX2541SQ3320E changing from 3600 to 3400 with an OSCin frequency of 100
MHz. In this case, ΔF = 200 (direction of frequency change does not matter), f
OSCin
= 100 MHz, and
OSC_FREQ=100. The calibration circuitry is run at a clock speed of CLK = 100 MHz / 4 = 25 MHz. When this
values are substituted in the formula, the resulting lock time is 218 μs. After this time, the VCO will be within
about 10 MHz of the final frequency and this final frequency error will settle out in an analog fashion. This final
frequency error can be slightly different depending on which option of the LMX2541 is being used.
Digital FSK Mode
The LMX2541 supports 2-level digital frequency shift keying (FSK) modulation. The bit rate is limited by the loop
bandwidth of the PLL loop. As a general rule of thumb, it is desirable to have the loop bandwidth at least twice
the bit rate. This is achieved by changing the N counter rapidly between two states. The fractional numerator and
denominator are restricted to a length of 12 bits. The 12 LSB’s of the numerator and denominator set the center
frequency, Fcenter, and the 10 MSB’s of the numerator set the frequency deviation, Fdev. The LMX2541 has the
ability to switch between two different numerator values based on the voltage at the DATA pin. When DATA is
low, the output frequency will be Fcenter – Fdev and when the DATA pin is high the output frequency will be
Fcenter + Fdev. A limitation of the FSK mode is the frequency deviation can not cause the N counter to cross
integer boundaries. When using FSK mode, the FDM bit needs to be set to zero.
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E