Datasheet

LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
www.ti.com SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
Maximum Possible Phase Detector Frequency (MHz)
f
VCO
ε
min
ORDER
(MHz) (ns)
ε = 3.5 ns ε = 5.5 ns ε = 7.5 ns ε = 9.5 ns ε = 11.5 ns ε = 13.5 ns
Min Min Min Min Min Min
All 0 0.0 (104, f
VCO
/ (104, f
VCO
/ (104, f
VCO
/ (87.0, f
VCO
/ (74.1, f
VCO
/ (64.5, f
VCO
/
12) 12) 12) 12) 12) 12)
400 4 20.0 FAIL FAIL FAIL FAIL FAIL FAIL
400 3 10.0 FAIL FAIL FAIL FAIL 26.7 26.7
400 2 5.0 FAIL 30.8 30.8 30.8 30.8 30.8
500 4 16.0 FAIL FAIL FAIL FAIL FAIL FAIL
500 3 8.0 FAIL FAIL FAIL 33.3 33.3 33.3
500 2 4.0 FAIL 38.5 38.5 38.5 38.5 38.5
600 4 13.3 FAIL FAIL FAIL FAIL FAIL 31.6
600 3 6.7 FAIL FAIL 40.0 40.0 40.0 40.0
600 2 3.3 46.2 46.2 46.2 46.2 46.2 46.2
1200 4 6.7 FAIL FAIL 63.2 63.2 63.2 63.2
1200 3 3.3 80.0 80.0 80.0 80.0 74.1 64.5
1200 2 1.7 92.3 92.3 92.3 87.0 74.1 64.5
1530 4 5.2 FAIL 80.3 80.3 80.3 74.1 64.5
1530 3 2.6 102.0 102.0 102.0 87.0 74.1 64.5
1530 2 1.3 104.0 104.0 104.0 87.0 74.1 64.5
1800 4 4.4 FAIL 91.8 91.8 87.0 74.1 64.5
1800 3 2.2 104.0 104.0 104.0 87.0 74.1 64.5
1800 2 1.1 104.0 104.0 104.0 87.0 74.1 64.5
2000 4 4.0 FAIL 100.0 100.0 87.0 74.1 64.5
2000 3 2.0 104.0 104.0 104.0 87.0 74.1 64.5
2000 2 1.0 104.0 104.0 104.0 87.0 74.1 64.5
3000 4 2.7 104.0 104.0 104.0 87.0 74.1 64.5
3000 3 1.3 104.0 104.0 104.0 87.0 74.1 64.5
3000 2 0.7 104.0 104.0 104.0 87.0 74.1 64.5
4000 4 2.0 104.0 104.0 104.0 87.0 74.1 64.5
4000 3 1.0 104.0 104.0 104.0 87.0 74.1 64.5
4000 2 0.5 104.0 104.0 104.0 87.0 74.1 64.5
In the previous table, consider the case of operating in integer mode with ORDER=0. For this case, lock detect
can theoretically work for all VCO frequencies provided that the phase detector frequency does not violate the
maximum possible value. For instance, it would be an invalid condition to operate in integer mode with a VCO
frequency of 900 MHz and a phase detector frequency of 100 MHz because 100 MHz exceeds the limit of 900
MHz/12 = 75 MHz. If the phase detector was lowered to 75 MHz to meet this restriction, then this condition would
be valid provided that the window size was programmed to be 9.5 ns or less.
Consider another example of a 400 MHz VCO frequency with a fourth order modulator. Because the minimum
window size of 20 ns is above the maximum programmable value of 13.5 ns, digital lock detect can not be used
in this configuration. If the modulator order was reduced to 2nd order, then it would function provided that the
phase detector frequency was less 30.8 MHz.
FSK - Frequency Shift Keying
This bit enables a binary FSK modulation mode using the PLL N counter. Consult the applications section for
more details.
FSK FSK Mode
0 Disabled
1 Enabled
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E