Datasheet

LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013 www.ti.com
DLOCK[2:0] - Controls for Digital Lock detect
This word controls operation of the digital lock detect function through selection of the window sizes (ε and δ). In
order to indicate the PLL is locked, there must be 5 consecutive phase detector output cycles in which the time
offset between the R and N counter outputs is less than ε. This will cause the Ftest/LD pin output to go high.
Once lock is indicated, it will remain in this state until the time offset between the R and N counter outputs
exceeds δ. For this device, ε and δ are the same. If the OSCin signal goes away, the digital lock detect circuit will
reliably indicate an unlocked condition. Consult the Functional Description for more details. A larger window size
makes the lock detect circuit less sensitive, but may be necessary in some situations to reduce chattering.
Window Size
DLOCK
(ε and δ)
0
3.5
(Default)
1 5.5
2 7.5
3 9.5
4 11.5
5 13.5
6 -7 Reserved
There are restrictions when using digital lock detect, based on the phase detector frequency (f
PD
), Modulator
Order (ORDER), and VCO frequency (f
VCO
). The first restriction involves a minimum window size (ε
min
), the
second one involves a maximum window size (ε
max
), and the third involves further restrictions on the maximum
phase detector frequency that are implied by the window size that is selected.
The first restriction involves the minimum window size (ε
min
). This minimum window size can not be greater than
the maximum programmable value of 13.5 ns for valid operation of the digital lock detect. Possible remedies for
this solution would be reducing the delta sigma order, using a higher VCO frequency and using a larger
VCO_DIV value, or using analog lock detect.
13.5 ns ≥ ε
min
= 2
ORDER-1
/ f
VCO
(5)
The second restriction is the maximum window size (ε
max
). If the calculated maximum window size is less than
the minimum programmable window size of 3.5 ns, then this indicates that the digital lock detect can not be used
in this condition. Possible remedies for this could be to decrease the phase detector frequency, use analog lock
detect, decrease the delta sigma order, or decrease the VCO frequency.
3.5 ns ≤ ε
max
= 1/f
PD
- ε
min
- 2 ns (6)
The third restriction comes from rearranging the equation for ε
max
.
f
PD
≤ 1 / ( ε
min
+ ε
max
+ 2 ns ) (7)
In addition to this restriction on the maximum phase detector rate, recall that there are also restrictions on the
maximum phase detector rate implied by the electrical specifications ( f
PD
≤ 104 MHz ) and by the minimum
continuous N divider value (f
PD
≤ f
VCO
/ N
Min
).
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LMX2541SQ3320E LMX2541SQ3740E