Datasheet
GND
VccBias
L2
0
GND
36
35
34
33
32 31 30 29 28
27
26
25
24
23
22
21
20
19
10
11 12 13
14 15 16 17 18
1
2
3
4
5
6
7
8
9
VregRFout
VccRFout
VregVCO
VrefVCO
GND
CE
ExtVCOin
VccPLL1
OSCin
VccCP1
Vtune
VccCP2
CPout
FLout
Ftest/LD
VccPLL2
OSCin*
VccOSCin
RFoutEN
VccFRAC
VregFRAC
GND
Bypass
RFout
NC
LE
CLK
DATA
VccDiv
L1
Lmid
VccVCO
VccDig
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
www.ti.com
Connection Diagram
Figure 1. 36-Pin NJK0036A Package (Top View)
PIN DESCRIPTIONS
Pin # Name Type Description
0 GND GND The DAP pad must be grounded.
1 GND GND
2 VregRFout LDO Output LDO Output for RF output buffer.
Supply
3 VccRFout Supply for the RF output buffer.
(LDO Input)
4 L1 NC Do not connect this pin.
5 Lmid NC Do not connect this pin.
6 L2 NC Do not connect this pin.
Supply
7 VccVCO Supply for the VCO.
(LDO Input)
8 VregVCO LDO Output LDO Output for VCO
9 VrefVCO LDO Bypass LDO Bypass
10 GND GND
Chip Enable.
11 CE CMOS
The device needs to be programmed for this pin to properly power down the device.
Optional input for use with an external VCO.
12 ExtVCOin RF Input
This pin should be AC coupled if used or left open if not used.
13 VccPLL1 Supply Power supply for PLL.
14 VccCP1 Supply Power supply for PLL charge pump.
15 Vtune High-Z Input Tuning voltage input to the VCO.
16 CPout Output Charge pump output.
17 FLout Output Fastlock output.
18 VccCP2 Supply Power supply for PLL charge pump.
19 VccPLL2 Supply Power supply for PLL.
4 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E