Datasheet

LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013 www.ti.com
Table 8. Register Map
The following table lists the registers as well as the order that they should be programmed. Register 7 is programmed first and the action of programming register R7 resets all the registers
after the LE pin is pulled to a low state. Register R0 is programmed last because it activates the VCO calibration. The one exception to this is when the VCO_DIV value is 4 or 5. Consult the
programming section on VCO_DIV for more details.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[27:0] C3 C2 C1 C0
R7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
VCO_DIV_OPT
R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1
[2:0]
R12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
R9 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1
R8 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 1 1 1 AC_TEMP_COMP[4:0] 1 0 0 0
RFOUT[1
R6 0 0 0 0 0 0 0 0 0 0 0 1 1 1 VCOGAIN[3:0] OUTTERM[3:0] DIVGAIN[3:0] 0 1 1 0
:0]
R5 1 0 1 FL_CPG[4:0] FL_RF_LF[2:0] FL_R3_LF[2:0] FL_TOC[13:0] 0 1 0 1
R4 C4_LF[3:0] C3_LF[3:0] R4_LF[2:0] R3_LF[2:0] VCO_DIV[5:0] OSC_FREQ[7:0] 0 1 0 0
PO
OS WE
FS CP FD CP MODE[1:
R3 0 0 DLOCK[2:0] DITH[1:0] ORDER[2:0] C MUX[3:0] CPG[4:0] XO R 0 0 1 1
K T M P 0]
_2X DO
WN
R2 0 0 0 0 0 1 DEN[21:0] 0 0 1 0
R1 0 0 0 0 PLL_NUM[21:16] PLL_N[17:12] PLL_R[11:0] 0 0 0 1
R0 PLL_NUM[15:0] PLL_N[11:0] 0 0 0 0
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