Datasheet

LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013 www.ti.com
Because of these considerations, the OSCin sensitivity needs to be measured in a closed loop test in such a way
that the internal frequency calibration is not distorting the measurement. To do this, a known frequency and
power level are set at the OSCin pin and the power level is changed until the PLL becomes more than 1 ppm off
frequency. The PLL_R divider is varied to maintain a phase detector frequency of 1 MHz to ensure that the PLL
loop does not become unstable. The frequency counter needs to be synchronized in frequency to the signal
generator. It is better to use a narrower loop bandwidth for this test because the phase noise of the PLL might
degrade when the OSCin power level gets to close to the sensitivity limits. Typically, a 0.1 uF capacitor is used
as a DC block for the signal at the OSCin pin. The sensitivity at the OSCin pin is measured with a single-ended
input.
This test can be run in internal VCO mode (MODE=0) or external VCO mode (MODE=1). When doing the test in
internal VCO mode, the part needs to be initially locked and then the R counter is programmed to adjust for the
OSCin frequency. However, in internal VCO mode, the PLL_N counter can not be programmed, because the
action of programming this counter activates the internal VCO frequecy calibration, which can interfere with the
test.
OSCin Slew Rate Tests
There are two methods that can be used to test the OSCin slew rate. One method is to use test equipment that
actually allows the user to vary the slew rate directly, but this type of equipment typically does not give the user
enough range of adjustability. Another method is to calculate the slew rate based on the slope of a sine wave of
known frequency and amplitude. For this method, the slew rate can be calculated from the frequency and peak
to peak amplitude of the OSCin signal as follows: Slew
OSCin
= 2 × π × f
OSCin
× Vpp
OSCin
FUNCTIONAL DESCRIPTION
The LMX2541 is a low power, high performance frequency synthesizer system which includes a PLL, Partially
Integrated Loop Filter, VCO, VCO Divider, and Programmable Output Buffer. There are three basic modes that
the device can be configured in: Full Chip Mode, External VCO Mode, and Divider Only Mode. Full chip mode is
intended to be used with the internal VCO and PLL. There is also the option of External VCO mode, which allows
the user to connect their own external VCO. Finally, there is Divider only, which is just the VCO divider and
output buffer. The active blocks for these modes are described below:
Available Blocks
Mode
Loop VCO Output
PLL VCO
Filter Divider Buffer
Full
Yes Yes Yes Yes Yes
Chip
External
Yes No No Yes Yes
VCO
Divider
No No No Yes Yes
Only
PLL Reference Oscillator Input Pins
There are three basic ways that the OSCin/OSCin* pins may be configured as shown in the table below:
Mode Description XO Bit
Crystal Device is used with a crystal oscillator 1
Single
Device is driven with a single-ended source, such as a TCXO. 0
Ended
Use this mode when driving with a differential signal, such as an LVDS
Differential 0
signal.
In addition to the way that the OSCin/OSCin* pins are driven, there are also bits that effect the frequency that the
chip uses. The OSC_FREQ word needs to be programmed correctly, or the VCO may have issues locking to the
proper frequency, since the VCO frequency calibration is based on this word.
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E