Datasheet
t
CES
t
CS
D19 D18 D17 D16
t
CH
t
CWH
t
CWL
D15 D0 C3 C2 C1 C0
MSB LSB
DATA
CLK
LE
t
ES
t
EWH
LMX2541SQ2060E, LMX2541SQ2380E
LMX2541SQ2690E, LMX2541SQ3030E
LMX2541SQ3320E, LMX2541SQ3740E
SNOSB31I –JULY 2009–REVISED FEBRUARY 2013
www.ti.com
Electrical Characteristics (continued)
(3.15 V ≤ V
CC
≤ 3.45 V, -40°C ≤ T
A
≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.)
Symbol Parameter Conditions Min Typ Max Units
10 kHz Offset -83.9
100 kHz Offset -108.3
f
RFout
=
Min VCO 1 MHz Offset -129.9
Frequency
10 MHz offset -150.6
20 MHz Offset -156.5
Phase Noise
L(f)
Fout
dBc/Hz
3740E
10 kHz Offset -81.6
100 kHz Offset -106.5
f
RFout
=
Max VCO 1 MHz Offset -127.7
Frequency
10 MHz Offset -148.6
20 MHz Offset -154.2
Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout,RFoutEN)
V
IH
High-Level Input Voltage 1.6 Vcc V
V
IL
Low-Level Input Voltage 0.4 V
I
IH
High-Level Input Current V
IH
= 1.75, XO = 0 -5 5 µA
I
IL
Low-Level Input Current V
IL
= 0 V , XO = 0 -5 5 µA
V
OH
High-Level Output Voltage I
OH
= 500 µA 2.0 V
V
OL
Low-Level Output Voltage I
OL
= -500 µA 0.0 0.4 V
I
Leak
Leakage Current Ftest/LD and FLout Pins Only -5 5 µA
MICROWIRE Timing
t
CE
Clock to Enable Low Time See Data Input Timing 25 ns
t
CS
Data to Clock Set Up Time See Data Input Timing 25 ns
t
CH
Data to Clock Hold Time See Data Input Timing 20 ns
t
CWH
Clock Pulse Width High See Data Input Timing 25 ns
t
CWL
Clock Pulse Width Low See Data Input Timing 25 ns
t
CES
Enable to Clock Set Up Time See Data Input Timing 25 ns
t
EWH
Enable Pulse Width High See Data Input Timing 25 ns
Serial Data Timing Diagram
There are several other considerations for programming:
• The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE
signal, the data is sent from the shift registers to an actual counter.
• A slew rate of at least 30 V/μs is recommended for the CLK, DATA, and LE signals.
• After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state.
• When using the part in Full Chip Mode with the Integrated VCO, LE should be kept high no more than 1 us
after the programming of the R0 register. Failure to do so may interfere with the digital VCO calibration.
• If the CLK and DATA lines are toggled while the in VCO is in lock , as is sometimes the case when these
lines are shared with other parts, the phase noise may be degraded during the time of this programming.
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Product Folder Links: LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E
LMX2541SQ3320E LMX2541SQ3740E