Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

LMX2541SQ2060E, LMX2541SQ2380E

LMX2541SQ2690E, LMX2541SQ3030E

LMX2541SQ3320E, LMX2541SQ3740E

www.ti.com

SNOSB31I –JULY 2009–REVISED FEBRUARY 2013

LMX2541 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO

Check for

Samples: LMX2541SQ2060E, LMX2541SQ2380E, LMX2541SQ2690E, LMX2541SQ3030E, LMX2541SQ3320E, LMX2541SQ3740E

FEATURES

DESCRIPTION

• Very Low RMS Noise and Spurs

The LMX2541 is an ultra low noise frequency

– -225 dBc/Hz Normalized PLL Phase Noise

synthesizer which integrates a high performance

– Integrated RMS Noise (100 Hz - 20 MHz)

delta-sigma fractional N PLL, a VCO with fully

integrated tank circuit, and an optional frequency

– 2 mrad (100 Hz - 20 MHz) at 2.1 GHz

divider. The PLL offers an unprecedented normalized

– 3.5 mrad (100 Hz - 20 MHz) at 3.5 GHz

noise floor of -225 dBc/Hz and can be operated with

• Ultra Low-Noise Integrated VCO

up to 104 MHz of phase-detector rate (comparison

frequency) in both integer and fractional modes. The

• External VCO Option (Internal VCO Bypassed)

PLL can also be configured to work with an external

• VCO Frequency Divider 1 to 63 (all values)

VCO.

• Programmable Output Power

The LMX2541 integrates several low-noise, high

• Up to 104 MHz Phase Detector Frequency

precision LDOs and output driver matching network to

• Integrated Low-Noise LDOs

provide higher supply noise immunity and more

consistent performance, while reducing the number of

• Programmable Charge Pump Output

external components. When combined with a high

• Partially Integrated Loop Filter

quality reference oscillator, the LMX2541 generates a

• Digital Frequency Shift Keying (FSK)

very stable, ultra low noise signal.

Modulation Pin

The LMX2541 is offered in a family of 6 devices with

• Integrated Reference Crystal Oscillator Circuit

varying VCO frequency range from 1990 MHz up to 4

• Hardware and Software Power Down

GHz. Using a flexible divider, the LMX2541 can

generate frequencies as low as 31.6 MHz. The

• FastLock Mode and VCO-Based Cycle Slip

LMX2541 is a monolithic integrated circuit, fabricated

Reduction

in a proprietary BiCMOS process. Device

• Analog and Digital Lock Detect

programming is facilitated using a three-wire

• 1.6 V Logic Compatibility

MICROWIRE interface that can operate down to 1.6

volts. Supply voltage ranges from 3.15 to 3.45 volts.

TARGET APPLICATIONS The LMX2541 is available in a 36 pin 6x6x0.8 mm

WQFN Package.

• Wireless Infrastructure (UMTS, LTE, WiMax)

• Broadband Wireless

• Wireless Meter Reading

• Test and Measurement

Device VCO Frequency

LMX2541SQ2060E 1990 - 2240

LMX2541SQ2380E 2200 - 2530

LMX2541SQ2690E 2490 - 2865

LMX2541SQ3030E 2810 - 3230

LMX2541SQ3320E 3130 - 3600

LMX2541SQ3740E 3480 - 4000

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (64 pages)

PAGE 1
LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.
PAGE 2
LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com System Diagram Clean Reference Clock Ultra-Clean Local Oscillator Dist. Dirty Input Clock PLL PLL LMK04000 LMX2541 (Clock Jitter Cleaner) (RF Synthesizer) LMX2541 Frequency Coverage 2060E 2380E 2690E 3030E 3320E 3740E VCO _DIV Start Stop Start Stop Start Stop Start Stop Start Stop Start Stop 1 1990.0 2240.0 2200.0 2530.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com Performance Characteristic VCO Phase Noise SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 What Makes it Better Operating in the lower frequency range of the VCO Why At the lower end of the tuning range, the VCO phase noise is less because the tuning gain is less. This provides better phase noise, even accounting for the difference in frequency.
PAGE 4
LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.
PAGE 5
LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 PIN DESCRIPTIONS (continued) Pin # Name Type Description Software controllable multiplexed CMOS output. Can be used to monitor PLL lock condition. 20 Ftest/LD Output 21 OSCin High-Z Input Oscillator input signal. If not being used with an external crystal, this input should be AC coupled.
PAGE 6
LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Package Thermal Resistance θJA θJC 9 Thermal Vias (Recommended for Most Reliable Solderability) 31.7 °C/W 7.3 °C/W 13 Thermal Vias (Compromise Between Solderability, Heat Dissipation, and Fractional Spurs) 30.3 °C/W 7.3 °C/W 16 Thermal Vias (Recommended for Optimal Heat Dissipation and Fractional Spurs) 29.8 °C/W 7.
PAGE 7
LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Electrical Characteristics (continued) (3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.) Symbol Parameter Conditions Min Typ Max Units ICPoutV Charge Pump Current vs. CP Voltage Variation 0.4 V < VCPout < Vcc - 0.4 TA = 25°C 4 % ICPoutT CP Current vs.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) (3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.
PAGE 9
LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Electrical Characteristics (continued) (3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.
PAGE 10
LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) (3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are at Vcc = 3.3 V, 25 C.) Symbol Parameter Conditions fRFout = Min VCO Frequency L(f)Fout Phase Noise 3740E fRFout = Max VCO Frequency Min Typ 10 kHz Offset -83.9 100 kHz Offset -108.3 1 MHz Offset -129.9 10 MHz offset -150.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Typical Performance Characteristics (Not Guaranteed) LMX2541SQ3740E Raw Phase Noise Measurement -80 PHASE NOISE (dBc/Hz) -85 -90 -95 -100 -105 Measured Noise -110 1/f Noise -115 Noise Floor -120 1.E+02 1.E+03 1.E+04 1.E+06 1.E+05 1.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (Not Guaranteed) (continued) LMX2541SQ3320E System Phase Noise -70 VI = 5.8 mRad (FPD = 50 MHz) PHASE NOISE (dBc/Hz) -80 -90 -100 VI = 5.1 mRad (OSCin Scaled to Freq.) -110 -120 -130 VI = 5.1 mRad (FPD = 100 MHz) -140 -150 -160 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Typical Performance Characteristics (Not Guaranteed) (continued) Divider Noise Floor vs. Divider Value (fVCO = 3700 MHz, Various values for VCO_DIV) -90 VCO_DIV = 1 PHASE NOISE (dBc/Hz) -100 VCO_DIV = 2 -110 VCO_DIV = 3 -120 VCO_DIV = 4 -130 VCO_DIV = 5 -140 VCO_DIV = 6 -150 -160 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (Not Guaranteed) (continued) PLL NORMALIZED NOISE FLOOR (dBc/Hz) PLL NORMALIZED NOISE FLOOR (dBc/Hz) PLL Normalized Noise Floor vs. OSCin Slew Rate (KPD = 32X) -206 -210 -214 -218 -222 -226 1 10 10 2 3 10 10 PLL Normalized Noise Floor vs.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Typical Performance Characteristics (Not Guaranteed) (continued) VCO Phase Noise Degradation vs. Temperature and Offset (VCO Relocked at Each Temperature Vcc = 3.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com The following plots show the trends in output power as a function of temperature, voltage, and frequency. For states where VCOGAIN and OUTTERM are not 12, the table below shows how the output power is modified based on these programmable settings. Output Power vs. Voltage (VCO_DIV = 1, VCOGAIN = 12, OUTTERM = 12, TA = 25°C (2)) Output Power vs.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Table 2. Change in Output Power in Bypass Mode as a Function of VCOGAIN and OUTTERM VCOGAIN OUTTERM 3 6 9 12 15 3 -9.7 -8.4 -7.9 -7.8 -7.9 6 -6.6 -4.5 -3.6 -3.4 -3.6 9 -5.7 -3.1 -1.7 -1.3 -1.3 12 -5.4 -2.5 -0.8 +0.0 +0.1 15 -5.3 -2.2 -0.3 +0.8 +1.1 Output Power vs.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Table 3. Change in Output Power in Divided Mode as a Function of DIVGAIN and OUTTERM(1) (continued) OUTTERM 3 -10.2 -6.1 -5.7 -5.5 -5.5 6 -9.8 -4.4 -2.4 -2.1 -2.0 9 -9.8 -4.3 -1.5 -0.7 -0.5 12 -9.9 -4.3 -1.4 +0.0 +0.2 15 -9.9 -4.4 -1.4 +0.3 +0.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Table 4. RFout Output Impedance vs. VCOGAIN (Bypass Mode) (1) (1) VCOGAIN=3 VCOGAIN=6 VCOGAIN=9 VCOGAIN=12 VCOGAIN=15 Freq. (MHz) Real Imaginary Real Imaginary Real Imaginary Real Imaginary Real Imaginary 50 3.8 2.1 5.5 1.9 7.3 1.8 9.5 1.7 10.1 1.7 100 4.8 4.1 6.1 3.9 7.8 3.7 9.8 3.6 10.3 3.6 200 5.4 5.7 6.8 6.0 8.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Table 5. RFout Output Impedance vs. OUTTERM (Bypass Mode) (1) (1) 20 OUTTERM=3 OUTTERM=6 OUTTERM=9 OUTTERM=12 TERM=15 Freq. (MHz) Real Imaginary Real Imaginary Real Imaginary Real Imaginary Real Imaginary 50 27.9 1.6 16.2 1.9 12.3 1.8 9.5 1.7 7.8 1.7 100 28.5 2.8 16.7 3.6 12.7 3.6 9.8 3.6 8.0 3.5 200 29.2 3.8 18.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Table 6. RFout Output Impedance vs. DIVGAIN (Divided Mode) (1) (1) DIVGAIN=3 DIVGAIN=6 DIVGAIN=9 DIVGAIN=12 DIVGAIN=15 Freq. (MHz) Real Imaginary Real Imaginary Real Imaginary Real Imaginary Real Imaginary 50 3.2 2.2 3.6 2.1 5.8 2.0 13.9 1.9 22.3 1.6 100 4.5 4.1 4.6 4.0 6.6 3.8 14.7 3.2 23.2 2.3 200 5.7 5.3 6.4 5.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Table 7. RFout Output Impedance vs. OUTTERM (Divided Mode) (1) Freq.(MHz) (1) 22 OUTTERM=3 OUTTERM=6 OUTTERM=9 OUTTERM=12 OUTTERM=15 Real Imaginary Real Imaginary Real Imaginary Real Imaginary Real Imaginary 50 44.1 -0.3 31.8 1.0 21.2 1.7 14.0 1.9 9.3 2.0 100 44.9 -2.2 32.8 0.7 22.1 2.5 14.8 3.2 10.0 3.5 200 43.2 -7.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 OSCin Sensitivity for Single-Ended SINE Wave 20 INPUT POWER (dBm) 10 Guaranteed Operating Range 0 -10 -20 -30 -40 1 10 100 1000 fOSCin (MHz) The above chart shows the typical sensitivity for a sine wave. Note that at lower frequencies, there is a constant slope that suggests that the part fails when the slew rate falls below 27 V/us.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com OSCin Input Impedance Marker 1: 50 MHz Marker 2: 100 MHz Marker 3: 500 MHz 1 XO = 1 4 2 3 Marker 4: 1000 MHz 2 Start 50 MHz Stop 1000 MHz XO = 0 4 3 Figure 24. OSCin (Normal Mode) OSCin (XO Mode) OSCin# (Normal Mode) Frequency (MHz) Real Imaginary Real Imaginary Real Imaginary 1 3945.3 2261.6 9452.3 2182.1 3975.5 2287.0 5 4846.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 ExtVCOin Input Impedance Marker 1: 100 MHz 7 8 Marker 2: 1 GHz Marker 3: 2 GHz 6 Marker 4: 3 GHz Marker 5: 4 GHz 1 5 Marker 6: 5 GHz Marker 7: 6 GHz 2 Marker 8: 7 GHz 3 4 Start 100 MHz Stop 7000 MHz Figure 25. Frequency Real Imaginary 100 627.9 -1532.3 200 193.8 -852.6 400 56.4 -434.5 600 31.3 -287.4 800 23.2 -212.9 1000 17.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com BENCH TEST SETUPS Charge Pump Currents Test Setup DC Blocking Capacitor 10 MHz SMA Cable OSCin Signal Generator Device Under Test Semiconductor Parameter Analyzer SMA Cable CPout Pin 3.3 V Evaluation Board Power Supply The charge pump is tested in external VCO mode (MODE=1), although it is no external VCO hooked up.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Charge Pump Current Definitions Figure 26.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Figure 29. Charge Pump Sink vs. Source Current Mismatch RFout Output Power Test Setup (1) 100 MHz SMA Cable OSCin Signal Generator Device Under Test SMA Cable Spectrum Analyzer Matching Network RFout Pin DC Blocking Capacitor 3.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 MHz typically has much better phase noise than a direct 20 MHz signal, if it comes from a signal generator. Another technique is to measure the noise of the reference source and then multiply it up and then subtract it from the measurement.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Input and Output Impedance Test Setup Calibrate for Open, Short, Load Here Network Analyzer Frequency Pin Device Under Test Evaluation Board Power Supply A network analyzer can be used to measure the input impedance of the OSCin and ExtVCOin pin as well as the output impedance of the RFout pin.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 ExtVCOin (NOT OSCin) Input Sensitivity Test Setup SMA Cable Signal Generator Matching Network ExtVCOin DC Blocking Capacitor SMA Cable Frequency Counter Device Under Test Ftest/LD Pin Evaluation Board Power Supply In order to measure the ExtVCOin Input sensitivity, the part is put in External VCO mode and a signal is applied to the ExtVCOin pin.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Because of these considerations, the OSCin sensitivity needs to be measured in a closed loop test in such a way that the internal frequency calibration is not distorting the measurement. To do this, a known frequency and power level are set at the OSCin pin and the power level is changed until the PLL becomes more than 1 ppm off frequency.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Word Name Function OSC_FREQ This needs to be set correctly if the internal VCO is used for proper calibration. OSC2X This allows the oscillator frequency to be doubled. The R divider is bypassed in this case. Higher slew rates tend to yield the best fractional spurs and phase noise, so a square wave signal is best for OSCin.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com fVCO = fPD × N = fOSCin × N / R (3) In order to the reduce the VCO tuning gain and therefore improve the VCO phase noise performance, the VCO frequency range is divided into many different frequency bands. This creates the need for frequency calibration in order to determine the correct frequency band given a desired output frequency.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 CE Pin POWERDOWN Bit Device State 0 Powered Up 1 Powered Down High The device can be programmed in the powerdown state. However, the VCO frequency needs to be changed when the device is powered up because the VCO calibration does not run in the powerdown state.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Parameter Symbol Calculation External Loop Filter Resistor R2pLF R2pLF = R2_LF / (K - 1) Lock Detect The Ftest/LD pin of the LMX2541 can be configured to output a signal that gives an indication for the PLL being locked. There are two styles of lock detect; analog and digital.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 General Programming Information The LMX2541 is programmed using several 32-bit registers used to control the LMX2541 operation. A 32-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Table 8. Register Map The following table lists the registers as well as the order that they should be programmed. Register 7 is programmed first and the action of programming register R7 resets all the registers after the LE pin is pulled to a low state. Register R0 is programmed last because it activates the VCO calibration.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Register R7 Although Register 7 has no elective bits to program, it is very important to program this register because the action of doing so with the bit sequence shown in the register map resets all the registers, including hidden registers with test bits that are not disclosed.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com RFOUT RFoutEN Pin RFout Pin State 2 Don't Care Enabled Low Disabled High Enabled 1 or 3 DIVGAIN[3:0], VCOGAIN[3:0], and OUTTERM[3:0] - Power Controls for RFout These three words may be programmed in a value from 0 to 15 and work in conjunction to control the output power level of the RFout pin.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com VCO_DIV VCO Output Divide Comments 4 Divide by 4 5 Divide by 5 Extra programming is required for divide by 4 and divide by 5 only. Refer to the Functional Description for more details. 6 Divide by 6 ... ...
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 C3_LF C3 (pF) 14 35 15 36 C4_LF[3:0] -- Value for C4 in the Internal Loop Filter This word controls the state of the internal loop filter resistor C4_LF when the device is Full Chip Mode.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com CPG Charge Pump State Typical Charge Pump Current (µA) 1 2X 200 2 3X 300 3 4X ... ... ... 31 32X 3200 MUX[3:0] -- Multiplexed Output for Ftest/LD Pin The MUX[3:0] word is used to program the output of the Ftest/LD Pin. This pin can be used for a general purpose I/O pin, a lock detect pin, and for diagnostic purposes.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 FDM - Extended Fractional Denominator Mode Enable Enabling this bit allows the fractional numerator and denominator to be expanded from 10 bits to 22 bits. In 10-bit mode, only the first 10 bits of the fractional numerator and denominator are considered. When using FSK mode, this bit has to be disabled.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com DLOCK[2:0] - Controls for Digital Lock detect This word controls operation of the digital lock detect function through selection of the window sizes (ε and δ). In order to indicate the PLL is locked, there must be 5 consecutive phase detector output cycles in which the time offset between the R and N counter outputs is less than ε.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com fVCO (MHz) SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Maximum Possible Phase Detector Frequency (MHz) εmin (ns) ORDER ε = 3.5 ns ε = 5.5 ns ε = 7.5 ns ε = 9.5 ns ε = 11.5 ns ε = 13.5 ns Min (104, fVCO / 12) Min (104, fVCO / 12) Min (87.0, fVCO / 12) Min (74.1, fVCO / 12) Min (64.5, fVCO / 12) All 0 0.0 Min (104, fVCO / 12) 400 4 20.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Register R2 This word contains all the bits of the fractional denominator. These bits apply if the device is being used fractional mode. PLL_DEN[21:0] -- Fractional Denominator These bits determine the fractional denominator. PLL_DEN[21:0] Fractional Denominator 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... . . . . . . . .
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Note that the N divider value has a minimum value, NMin, which is implied by the modulator order. NMin is 12 for integer mode and a first order modulator, 13 for a 2nd order modulator,15 for a third order modulator, and 19 for a fourth order modulator.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Figure 31. External VCO Mode, Single-Ended OSCin, RFout Pin not Used 51: 51: +3.3V Ferrite 0.1 PF 0.1 PF Microcontroller +3.3V Ferrite +3.3V VccPLL2 4.7: 0.1 PF Bypass VccPLL1 VccFRAC Ferrite 0.1 PF VregFRAC +3.3V VccBias VccOSCin OSCin* OSCin 1 PF Ftest/LD CE LE DATA CLK RFoutEN +3.3V Ferrite VccCP1 VrefVCO VregVCO Ferrite +3.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 50: Figure 32. Single-Ended Operation LMX2541 OSCin 0.1 PF 0.1 PF 50: OSCin* For differential operation, as is the case when using an LVDS or LVPECL driver, a 100 Ω resistor is placed across the OSCin/OSCin* traces Figure 33. Differential Operation LMX2541 0.1 PF 100: OSCin OSCin* 0.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com Fractional Spurs Primary Fractional Spurs The primary fractional spurs occur at multiples of the channel spacing and can change based on the fraction. For instance, if the phase detector frequency is 10 MHz, and the channel spacing is 100 kHz, then this could be achieved using a fraction of 1/100.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 Table 10. Change in Current Consumption in Bypass Mode as a Function of VCOGAIN and OUTTERM VCOGAIN OUTTERM 3 6 9 12 15 3 -26.0 -22.3 -18.6 -15.1 -11.8 6 -18.5 -15.5 -12.6 -9.7 -6.9 9 -11.1 -9.0 -6.9 -4.7 -2.5 12 -3.8 -2.6 -1.4 +0.0 +1.5 15 +3.3 +3.7 +4.0 +4.5 +5.3 Table 11.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 www.ti.com 4. Design the Loop Filter 5. Determine the Modulator Order 6. Determine Dithering and Potential Larger Equivalent Fractional Value External VCO Mode The LMX2541 also has provisions to be driven with an external VCO as well.
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LMX2541SQ2060E, LMX2541SQ2380E LMX2541SQ2690E, LMX2541SQ3030E LMX2541SQ3320E, LMX2541SQ3740E www.ti.com SNOSB31I – JULY 2009 – REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision H (February 2013) to Revision I • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) LMX2541SQX3740E/NOPB ACTIVE Package Type Package Pins Package Drawing Qty WQFN NJK 36 2500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU SN Level-3-260C-168 HR (4) -40 to 85 413740E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMX2541SQ2060E/NOPB WQFN NJK 36 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 LMX2541SQ2380E/NOPB WQFN NJK 36 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 LMX2541SQ2690E/NOPB WQFN NJK 36 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMX2541SQX2380E/NOP B WQFN NJK 36 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 LMX2541SQX2690E/NOP B WQFN NJK 36 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 LMX2541SQX3030E/NOP B WQFN NJK 36 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 LMX2541SQX3320E/NOP B WQFN NJK 36 2500 330.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMX2541SQE2690E/NOP B WQFN NJK 36 250 213.0 191.0 55.0 LMX2541SQE3030E/NOP B WQFN NJK 36 250 213.0 191.0 55.0 LMX2541SQE3320E/NOP B WQFN NJK 36 250 213.0 191.0 55.0 LMX2541SQE3740E/NOP B WQFN NJK 36 250 213.0 191.0 55.0 LMX2541SQX2060E/NOP B WQFN NJK 36 2500 367.0 367.0 38.0 LMX2541SQX2380E/NOP B WQFN NJK 36 2500 367.
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MECHANICAL DATA NJK0036A SQA36A (Rev A) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.