LMX2531LQ2820E Evaluation Board Operating Instructions National Semiconductor Corporation Timing Devices Business Group 10333 North Meridian Suite 400 Indianapolis, IN 46290 LMX25312820EVAL Instructions Rev 6.24.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Table of Contents Table of Contents ................................................................................................................ 2 Loop Filter .......................................................................................................................... 3 Quick Setup............................................................................................................
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Loop Filter Loop Bandwidth 14 kHz Kφ 1440 uA (16X) Phase Margin 54.1 ° FPD 10 MHz Crystal Frequency 10 MHz Output Frequency 2710 to 2925 MHz (DIV2=0) 1355 to 1462 MHz (DIV2=1) Supply Voltage 3.0 Volts VCO Gain 12 to 28 MHz/Volt CPout 20 KΩ 20 KΩ VCO 100 nF 100 pF 100 pF 1 KΩ open Vtune Quick Setup • • • • • • • Install the CodeLoader software which is available at www.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Troubleshooting Software does not communicate with the evaluation boards LPT or USB Mode • Ensure a valid signal is presented to the OSCin connector. If a signal generator is used, ensure the RF is ON. • Consult the CodeLoader instructions for more detailed information on communication issues.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Far-out Phase noise is worse than evaluation board instructions show • • Ensure the measurement equipment noise floor is not limiting the measurement. For spectrum analyzers, the noise floor at a particular setting can be measured by removing the RF input signal If the settings are changed from what the board was designed for, ensure the delta-sigma modulator is not increasing the far-out noise.
Output Frequency = 2820.25 MHz Internal Divide by 2 Disabled (DIV2=0) Output Frequency = 1410.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Fout = ~2710 MHz Free-Running VCO Phase Noise (Internal Divide by 2 Disabled) The plots to the left show the true phase noise capability of the VCO. In order to take these plots, the E5052 phase nose analyzer was used. The method was to lock the PLL to the proper frequency, then Fout = ~2820 MHz disable the EN_PLLLDO2, EN_PLL, EN_PLLLDO1, EN_DIGLDO, and EN_OSC bits.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Fout = ~1355 MHz (~2710 MHz/2) Free-Running VCO Phase Noise (Internal Divide by 2 Enabled) The plots to the left show the true phase noise capability of the VCO. In order to take these plots, the E5052 phase nose analyzer was used. The method was to lock the PLL to the proper frequency, then disable the Fout = ~1410 MHz (~2820 MHz/2) EN_PLLLDO2, EN_PLL, EN_PLLLDO1, EN_DIGLDO, and EN_OSC bits.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Fractional Spurs (Internal Divide by 2 Disabled) The -58.9 dBc fractional spur at 250 kHz offset is at a worst case frequency of 2710.25 MHz. The -76.0 dBc sub-fractional spur at 125 kHz offset is also visible. Worst case channels occur at exactly one channel spacing above or below a multiple of the crystal frequency. The -67.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Fractional Spurs (Internal Divide by 2 Enabled) The -66.2 dBc fractional spur at 250 kHz offset is at a worst case frequency of 1355.125 MHz. The -82.2 dBc sub-fractional spur at 125 kHz offset is also visible. The -72.6 dBc fractional spur at 250 kHz offset is at a worst case frequency of 1410.125 MHz. The -56.7 dBc sub-fractional spur at 125 kHz offset is also visible. The -68.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Integer Spurs (Internal Divide by 2 Disabled) The integer spur at 10 MHz offset at an Fout frequency of 2710 MHz is -83.5 dBc. The integer spur at 10 MHz offset at an Fout frequency of 2820 MHz is -81.8 dBc. The integer spur at 10 MHz offset at an Fout frequency of 2920 MHz is -86.0 dBc.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Integer Spurs (Internal Divide by 2 Enabled) The integer spur at 10 MHz offset at an Fout frequency of 1355 MHz is -82.6 dBc. The integer spur at 10 MHz offset at an Fout frequency of 1410 MHz is -80.3 dBc. The integer spur at 10 MHz offset at an Fout frequency of 1460 MHz is -80.4 dBc.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S In-band Factional Spurs Integer Spurs (Internal Divide by 2 Disabled) The In-band fractional spur at 5 kHz offset at an Fout frequency of 2710.005 MHz is -29.8 dBc. ORDER = 4th Order Modulator Fractional numerator = 500 Fractional denominator = 1,000,000 The In-band fractional spur at 5 kHz offset at an Fout frequency of 2820.005 MHz is -33.7 dBc.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S In-band Factional Spurs Integer Spurs (Internal Divide by 2 Enabled) The In-band fractional spur at 5 kHz offset at an Fout frequency of 1355.0025 MHz is -38.9 dBc. ORDER = 4th Order Modulator Fractional numerator = 500 Fractional denominator = 1,000,000 The In-band fractional spur at 5 kHz offset at an Fout frequency of 1410.0025 MHz is -41.8 dBc. See inter-modulation spur note on next page.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Inter-modulation Spurs The LMX2531 features an output divider which may divide the VCO frequency by two. The result is an Fout frequency half the VCO frequency. When this VCO divider is enabled a spur will occur between a multiple of the phase detector frequency and the Fout frequency. In the example below the phase detector frequency (FPD) is 10 MHz. The VCO frequency is 2820.005 MHz.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CodeLoader Settings Select Device CodeLoader runs many devices. When CodeLoader is first started, it is necessary to select the correct device.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Select Mode There can be different modes defined for a particular part. A mode can be recalled easily from the menu. This restores bit settings and frequencies, but not the Port Setup information. For the CodeLoader program, the default reference oscillator used for these instructions was 10 MHz, but there is a mode for a 61.44 MHz oscillator as well.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bits/Pins The Bits/Pins tab displays many of the bits used to program the part. Right mouse click any bit to view more information about what this does.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL/VCO The PLL/VCO tab shows all the important PLL controls. Reference Oscillator should be programmed to the reference frequency connected to the OSCin of the evaluation board. R Counter, Phase Detector Frequency, N Counter, and Charge Pump Gain should be set to provide the desired output frequency with an optimized loop filter.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Registers The Registers tab shows the literal bits that are being sent to the part. These are the registers every time the PLL is loaded by using the menu command or Ctrl+L. R5 (INIT1) and R5 (INIT 2) are just the R5 register being used to properly initialize the part. So a single Ctrl+L will load the part.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Port Setup The port setup tells CodeLoader what information goes where. If this is wrong, the part will not program. Although LPT1 is usually correct, CodeLoader does NOT automatically detect the correct port. On some laptops, it may be LPT3.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Schematic C6 POWER Vcc R1 Vcc 1 3 5 7 R2 2 4 6 8 VccVCO OSCin C2 R3 C1 R6 VccBUF C3 Ftest/LD VccPLL C7 C4 VccDIG C10 C11 C100 C9 VccDIG NC GND NC NC NC/VregBUF NC DATA CLK VccPLL VregPLL1 FLout CPout Vtune VccBUF Fout GND GND 27 26 25 24 23 22 21 20 19 R17 LE CE NC NC NC NC VccVCO VregVCO VrefVCO R11 R10 R9 C8 R8 Vcc 2 4 6 8 10 TRIGGER GND FRAME 1 3 5 7 9 uWIRE Note tha
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G Bill of Materials Bill of Materials Item QTY Manufacturer I N S T R U C T I O N S LMX2531_HF Part # Size Tol Voltage Material 20 Revision 3.28.
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G Top Layer 24 I N S T R U C T I O N S
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Mid Layer 1 "Ground Plane" (15 mils below top FR4 layer) 25
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G Mid Layer 2 "Power" 26 I N S T R U C T I O N S
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bottom Layer "Signal" Note: Total Board Thickness = 61 mils 27
L M X 2 5 3 1 L Q 2 8 2 0 E E V A L U A T I O N B O A R D O P E R A T I N G Top Build Diagram 28 I N S T R U C T I O N S
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