LMX2531LQ2265E Evaluation Board Operating Instructions National Semiconductor Corporation Wireless Communications, RF Products Group 2900 Semiconductor Dr. MS A2-600 Santa Clara, CA, 95052-8090 LMX2531LQ2265EFPEB Rev 1.19.
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S TABLE OF CONTENTS GENERAL DESCRIPTION ............................................................................................................................... 3 LOOP FILTER ................................................................................................................................................ 3 PHASE NOISE ....................................................................
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S General Description The LMX2531LQ2265E Evaluation Board simplifies evaluation of the LMX2531LQ2265E PLL/VCO synthesizer system. The board enables all performance measurements with no additional support circuitry. The evaluation board consists of a LMX2531LQ2265E device, and a cable assembly. The cable assembly is bundled with the evaluation board for connecting to a PC through the parallel printer port.
Output Frequency = 2264 MHz Internal Divide by 2 Disabled (DIV2=0) Output Frequency = 1132 MHz Internal Divide by 2 Enabled (DIV2=1) L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N Phase Noise 4 B O A R D O P E R A T I N G I N S T R U C T I O N S
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Phase Noise with Narrow Loop Filter Output Frequency = 2264 MHz Internal Divide by 2 Disabled (DIV2=0) Output Frequency = 1132 MHz Internal Divide by 2 Enabled (DIV2=1) (This is the most accurate measurement of the VCO phase noise) 5
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Spurs (Internal Divide by 2 Disabled) Spur at 200 kHz offset at a worst case frequency of 2150.2 MHz is -86.9 dBc. Worst case channels occur at exactly one channel spacing above or below a multiple of the crystal frequency (10 MHz). Spur at 200 kHz offset at a worst case frequency of 2270.2 MHz is -86.5 dBc. Spur at 200 kHz offset at a worst case frequency of 2380.2 MHz is -82.1 dBc.
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Spurs (Internal Divide by 2 Enabled) Spur at 200 kHz offset at a frequency of 1075.1 MHz is –89.6 dBc. Since this mode uses the divide by 2 mode, the channel spacing here is actually 100 kHz. The spur at 100 kHz could be eliminated by doubling the channel spacing before the divider. The reason that the spur at 200 kHz is shown is to illustrate theoretical 6 dB impact of the divider.
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CodeLoader Settings For the CodeLoader program, the default reference oscillator used for these instructions was 10 MHz, but there is a mode for a 61.44 MHz oscillator as well. If the bits become scrambled, their original state may be recalled by choosing the appropriate mode. Note that if the internal divide by 2 is enabled, the VCO frequency still reflects the VCO frequency before the divide by 2.
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S CodeLoader is set up to load the registers and initialize the part in the correct way. R5 (INIT1) and R5 (INIT 2) are just the R5 register being used to properly initialize the part. So a single CNT+L should load the part. The port setup tells CodeLoader what information goes where. If this is wrong, the part will not program.
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Schematic 2 3 R2 2 4 6 8 C2 R3 C1 D C3 VccPLL C7 C4 VccDIG C19 36 35 34 33 32 31 30 29 28 C23 C R22 VccPLL Vr egDIG NC GND Test OSCin* OSCin Ftest/LD NC Vr egPLL2 R24 R2pLF C24 C105 R23 C18 VccDIG C10 C100 C11 R17 VccDIG NC GND NC NC VregBUF NC DATA CLK VccPLL VregPLL1 FLout CPout Vtune VccBUF Fout GND GND 27 26 25 24 23 22 21 20 19 LE CE NC NC NC NC VccVCO Vr egVCO Vr ef V
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G Bill of Materials Item QTY Manufacturer I N S T R U C T I O N S LMX2531EB Part # Size Tol Voltage Material Value Designators Open Capacitors C2pLF, C2, C3, C4, C5, C9, C11, C14, C17, C18, C19, C21, C24, C100, C101, C102, C103, C104, C105 6 Open Resistors R7, R8, R17, R19, R21, R24 1 Open Miscellaneous Ftest/LD C0G 47pF C1_LF 19 0 1 Revision 1/3/2006 n/a 1 Kemet C0603C470J5GAC 603 5% 50V 2 1 Keme
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G Top Layer 12 I N S T R U C T I O N S
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Mid Layer 1 "Ground Plane" (15 Mils Down FR4) 13
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Mid Layer 2 "Power" 14
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bottom Layer "Signal" Note: Total Board Thickness = 61 mils 15
L M X 2 5 3 1 L Q 2 2 6 5 E E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Top Build Diagram 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
