Datasheet

LMV931-N, LMV931-N-Q1, LMV932-N, LMV932-N-Q1
LMV934-N, LMV934-N-Q1
www.ti.com SNOS993M –NOVEMBER 2001–REVISED NOVEMBER 2013
APPLICATION NOTE
INPUT AND OUTPUT STAGE
The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV931-N/LMV932-
N/LMV934-N use a complimentary PNP and NPN input stage in which the PNP stage senses common mode
voltage near V
−
and the NPN stage senses common mode voltage near V
+
. The transition from the PNP stage to
NPN stage occurs 1V below V
+
. Since both input stages have their own offset voltage, the offset of the amplifier
becomes a function of the input common mode voltage and has a crossover point at 1V below V
+
.
This V
OS
crossover point can create problems for both DC and AC coupled signals if proper care is not taken.
Large input signals that include the V
OS
crossover point will cause distortion in the output signal. One way to
avoid such distortion is to keep the signal away from the crossover. For example, in a unity gain buffer
configuration and with V
S
= 5V, a 5V peak-to-peak signal will contain input-crossover distortion while a 3V peak-
to-peak signal centered at 1.5V will not contain input-crossover distortion as it avoids the crossover point.
Another way to avoid large signal distortion is to use a gain of −1 circuit which avoids any voltage excursions at
the input terminals of the amplifier. In that circuit, the common mode DC voltage can be set at a level away from
the V
OS
cross-over point. For small signals, this transition in V
OS
shows up as a V
CM
dependent spurious signal in
series with the input signal and can effectively degrade small signal parameters such as gain and common mode
rejection ratio. To resolve this problem, the small signal should be placed such that it avoids the V
OS
crossover
point. In addition to the rail-to-rail performance, the output stage can provide enough output current to drive 600Ω
loads. Because of the high current capability, care should be taken not to exceed the 150°C maximum junction
temperature specification.
INPUT BIAS CURRENT CONSIDERATION
The LMV931-N/LMV932-N/LMV934-N family has a complementary bipolar input stage. The typical input bias
current (I
B
) is 15nA. The input bias current can develop a significant offset voltage. This offset is primarily due to
I
B
flowing through the negative feedback resistor, R
F
. For example, if I
B
is 50nA and R
F
is 100kΩ, then an offset
voltage of 5mV will develop (V
OS
= I
B
x R
F
). Using a compensation resistor (R
C
), as shown in Figure 28, cancels
this effect. But the input offset current (I
OS
) will still contribute to an offset voltage in the same manner.
Figure 28. Canceling the Offset Voltage due to Input Bias Current
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMV931-N LMV931-N-Q1 LMV932-N LMV932-N-Q1 LMV934-N LMV934-N-Q1