Datasheet

ESD
R
1
IN
+
ESD
D
1
D
2
R
2
ESD
ESD
V
-
V
+
IN
-
+
-
V
+
V
-
V
OUT
V
+
V
-
LMV841, LMV842, LMV844
www.ti.com SNOSAT1G –OCTOBER 2006–REVISED FEBRUARY 2013
APPLICATION INFORMATION
INTRODUCTION
The LMV841/LMV842/LMV844 are operational amplifiers with near-precision specifications: low noise, low
temperature drift, low offset, and rail-to-rail input and output. Possible application areas include instrumentation,
medical, test equipment, audio, and automotive applications.
Its low supply current of 1mA per amplifier, temperature range of −40°C to 125°C, 12V supply with CMOS input,
and the small SC70 package for the LMV841 make the LMV841/LMV842/LMV844 a unique op amp family and a
perfect choice for portable electronics.
INPUT PROTECTION
The LMV841/LMV842/LMV844 have a set of anti-parallel diodes D
1
and D
2
between the input pins, as shown in
Figure 37. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the
amount of differential input voltage that is allowed on the input pins.
A differential signal larger than one diode voltage drop can damage the diodes. The differential signal between
the inputs needs to be limited to ±300mV or the input current needs to be limited to ±10mA.
Note that when the op amp is slewing, a differential input voltage exists that forward biases the protection diodes.
This may result in current being drawn from the signal source. While this current is already limited by the internal
resistors R
1
and R
2
(both 130Ω), a resistor of 1kΩ can be placed in the feedback path, or a 500Ω resistor can be
placed in series with the input signal for further limitation.
Figure 37. Protection Diodes between the Input Pins
INPUT STAGE
The input stage of this amplifier consists of both a PMOS and an NMOS input pair to achieve a rail-to-rail input
range. For input voltages close to the negative rail, only the PMOS pair is active. Close to the positive rail, only
the NMOS pair is active. In a transition region that extends from approximately 2V below V
+
to 1V below V
+
, both
pairs are active, and one pair gradually takes over from the other. In this transition region, the input-referred
offset voltage changes from the offset voltage associated with the PMOS pair to that of the NMOS pair. The input
pairs are trimmed independently to guarantee an input offset voltage of less then 0.5 mV at room temperature
over the complete rail-to-rail input range. This also significantly improves the CMRR of the amplifier in the
transition region. Note that the CMRR and PSRR limits in the tables are large-signal numbers that express the
maximum variation of the amplifier's input offset over the full common-mode voltage and supply voltage range,
respectively. When the amplifier's common-mode input voltage is within the transition region, the small signal
CMRR and PSRR may be slightly lower than the large signal limits.
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Product Folder Links: LMV841 LMV842 LMV844