Datasheet

V
IN
+
-
+V
CC
R
1
1k:
R
2
1M:
C1
10PF
V
OUT
-
+
V
A
V
B
R
EXT
LOGIC
OUT
LMV7275
+
-
1k:
1k:
LOGIC
IN
LMV7271
www.ti.com SNOSA56H –FEBRUARY 2003–REVISED FEBRUARY 2013
Figure 33. Logic Level Shifter
POSITIVE PEAK DETECTOR
A positive peak detect circuit is basically a comparator operated in a unity gain follower configuration, with a
capacitor as a load to maintain the highest voltage. A diode is added at the output to prevent the capacitor from
discharging through the pull-up resistor, and a 1MΩ resistor added in parallel to the capacitor to provide a high
impedance discharge path. When the input V
IN
increases, the inverting input of the comparator follows it, thus
charging the capacitor. When it decreases, the cap discharges through the 1MΩ resistor. The decay time can be
modified by changing the resistor. The output should be accessed through a follower circuit to prevent loading.
Figure 34. Positive Peak Detector
OR'ING THE OUTPUT
Since the output is an unconnected NMOS drain, many drains can be tied together, pulled up to V
DD
by a single
resistor to provide an output OR'ing function. If any of the comparator outputs is pulled low the output V
O
goes
down.
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